Inventor
CLINE LESLIE E
US25 patents
⚠️ This page may combine multiple inventors who share the name “CLINE LESLIE E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
19 patentsUS7149909B2Dec 12, 2006
Power management for an integrated graphics device
INTEL CORP71 citations96
US6704877B2Mar 9, 2004
Dynamically changing the performance of devices in a computer platform
INTEL CORP68 citations96
US6738068B2May 18, 2004
Entering and exiting power managed states without disrupting accelerated graphics port transactions
INTEL CORP57 citations94
US7523327B2Apr 21, 2009
System and method of coherent data transfer during processor idle states
INTEL CORP19 citations92
US7281074B2Oct 9, 2007
Method and apparatus to quiesce USB activities using interrupt descriptor caching and asynchronous notifications
INTEL CORP31 citations92
US6988211B2Jan 17, 2006
System and method for selecting a frequency and voltage combination from a table using a selection field and a read-only limit field
INTEL CORP45 citations92
US6976181B2Dec 13, 2005
Method and apparatus for enabling a low power mode for a processor
INTEL CORP34 citations92
US6871252B1Mar 22, 2005
Method and apparatus for logical detach for a hot-plug-in data bus
INTEL CORP20 citations92
US7340550B2Mar 4, 2008
USB schedule prefetcher for low power
INTEL CORP19 citations90
US6802018B2Oct 5, 2004
Method and apparatus to directly access a peripheral device when central processor operations are suspended
INTEL CORP21 citations87
US6748548B2Jun 8, 2004
Computer peripheral device that remains operable when central processor operations are suspended
INTEL CORP33 citations87
US7472289B2Dec 30, 2008
Audio noise mitigation for power state transitions
INTEL CORP9 citations84
US7343502B2Mar 11, 2008
Method and apparatus for dynamic DLL powerdown and memory self-refresh
INTEL CORP17 citations84
US7069367B2Jun 27, 2006
Method and apparatus for avoiding race condition with edge-triggered interrupts
INTEL CORP6 citations74
US7373534B2May 13, 2008
Reducing storage data transfer interference with processor power management
INTEL CORP5 citations63
US7231468B2Jun 12, 2007
Future activity list for peripheral bus host controller
INTEL CORP3 citations63
US7225347B2May 29, 2007
Method and apparatus for enabling a low power mode for a processor
INTEL CORP4 citations63
US7027057B2Apr 11, 2006
Entering and exiting power managed states without disrupting accelerated graphics port transactions
INTEL CORP2 citations60
US7884499B2Feb 8, 2011
Intervention of independent self-regulation of power consumption devices
INTEL CORP1 citations49
CIRRUS LOGIC INC
5 patentsUS5630171AMay 13, 1997
Translating from a PIO protocol to DMA protocol with a peripheral interface circuit
CIRRUS LOGIC INC44 citations95
US5603052AFeb 11, 1997
Interface circuit for transferring data between host and mass storage by assigning address in the host memory space and placing the address on the bus
CIRRUS LOGIC INC25 citations91
US5592682AJan 7, 1997
Interface circuit for transferring data between host device and mass storage device in response to designated address in host memory space assigned as data port
CIRRUS LOGIC INC23 citations91
US5826107AOct 20, 1998
Method and apparatus for implementing a DMA timeout counter feature
CIRRUS LOGIC INC19 citations88
US5655145AAug 5, 1997
Peripheral interface circuit which snoops commands to determine when to perform DMA protocol translation
CIRRUS LOGIC INC14 citations81