Inventor

RAO G R MOHAN

US117 patents

⚠️ This page may combine multiple inventors who share the name “RAO G R MOHAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAO G R MOHAN

CIRRUS LOGIC INC

Fast cycle time-low latency dynamic random access memories and systems and methods using the same

Memory architecture and devices, systems and methods utilizing the same

Memory with pipelined accessed and priority precharge

Dynamic random access memory with a normal precharge mode and a priority precharge mode

Pipelined address memories, and systems and methods using the same

Low pin count - wide memory devices using non-multiplexed addressing and systems and methods using the same

Single chip controller-memory device and a memory architecture and methods suitable for implementing the same

Single chip controller-memory device including feature-selectable bank I/O and architecture and methods suitable for implementing the same

Memories with programmable address decoding and systems and methods using the same

Memory banks with pipelined addressing and priority acknowledging and systems and methods using the same

Multibank -- multiport memories and systems and methods using the same

Multi-bank memory system and method having addresses switched between the row and column decoders in different banks

Pipelined address memories, and systems and methods using the same

Multiple-bank memory architecture and systems and methods using the same

Systems and methods for implementing inter-device cell replacements

Memory devices with selectable access type and methods using the same

Pipeland address memories, and systems and methods using the same

Single chip controller-memory device and a memory architecture and methods suitable for implementing the same

Display controller with integrated half frame buffer and systems and methods using the same

Low pin count-wide memory devices and systems and methods using the same

TEXAS INSTRUMENTS INC

Semiconductor read/write memory array having serial access

Double level polysilicon series transistor cell

Semiconductor integrated circuit memory device with both serial and random access arrays

Method of making N-channel MOS integrated circuits

Semiconductor integrated circuit with implanted resistor element in polycrystalline silicon layer

Method of making double level polysilicon series transistor devices

High performance dynamic sense amplifier voltage boost for row address lines

Semiconductor read/write memory array having high speed serial shift register access

Semiconductor integrated circuit with implanted resistor element in polycrystalline silicon layer

SILICON AQUARIUS INC

DRAM with integral SRAM and arithmetic-logic units

Multiprocessor system with integrated memory

Multi-port DRAM with integrated SRAM and systems and methods using the same

Dram with integral sram comprising a plurality of sets of address latches each associated with one of a plurality of sram

Methods and systems for maintaining data locality in a multiple memory bank system having DRAM with integral SRAM

Dual port random access memories and systems using the same

Methods and circuits for single-memory cell multivalue data storage

Non-volatile and memory fabricated using a dynamic memory process and method therefor

Arrays of two-transistor, one-capacitor dynamic random access memory cells with interdigitated bitlines

RAO G R MOHAN

Semiconductor devices with graded dopant regions

Lifetime mixed level non-volatile memory system

Nonvolatile memory systems with embedded fast read and write memories

Nonvolatile memory systems with embedded fast read and write memories

Data security and digital rights management system

GREENTHREAD LLC

Lifetime mixed level non-volatile memory system

Lifetime mixed level non-volatile memory system

S AQUA SEMICONDUCTOR LLC

Pipelined semiconductor memories and systems

SILICON AQUARIUS

Methods and circuits for single-memory dynamic cell multivalue data storage

DATASECURE LLC

Posted precharge and multiple open-page RAM architecture

CIRRUS LOGIC INC E

Memory architecture using content addressable memory, and systems and methods using the same

VERVAIN LLC

Lifetime mixed level non-volatile memory system