Inventor

MAZURE CARLOS

FR54 patents

⚠️ This page may combine multiple inventors who share the name “MAZURE CARLOS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MAZURE CARLOS

SOITEC SILICON ON INSULATOR

Semiconductor structure and methods for fabricating same

Forming structures that include a relaxed or pseudo-relaxed layer on a substrate

Method of manufacturing a free-standing substrate made of monocrystalline semi-conductor material

Method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate

Method for recycling a substrate

Arrays of transistors with back control gates buried beneath the insulating film of a semiconductor-on-insulator substrate

Nano-sense amplifier

Forming structures that include a relaxed or pseudo-relaxed layer on a substrate

Method for direct bonding two semiconductor substrates

Method for manufacturing a free-standing substrate made of monocrystalline semiconductor material

Method for transferring a thin layer including a controlled disturbance of a crystalline structure

Method of fabricating a hybrid substrate

Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same

Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same

Substrate having a charged zone in an insulating buried layer

Nano-sense amplifier

Methods and structures for relaxation of strained layers

Low-cost double-structure substrates and methods for their manufacture

Low cost substrates and method of forming such substrates

Low-cost substrates having high-resistivity properties and methods for their manufacture

Method for producing a semiconductor substrate

Film taking-off method

Forming structures that include a relaxed or pseudo-relaxed layer on a substrate

Method of treating interface defects in a substrate

Substrate production method and substrate including amorphization and recrystallizing a top region

MAZURE CARLOS

DRAM memory cell having a vertical bipolar injector

SRAM-type memory cell

Pseudo-inverter circuit on SeOI

Device having a contact between semiconductor regions through a buried insulating layer, and process for fabricating said device

Method for manufacturing a semiconductor substrate

Flash memory cell on SeOI having a second control gate buried under the insulating layer

Pseudo-inverter circuit on SeOI

Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer

Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer

Devices and methods for comparing data in a content-addressable memory

Memory cell with a channel buried beneath a dielectric layer

Bonded semiconductor structures and method of forming same

NGUYEN BICH-YEN

Multi-layer structures and process for fabricating semiconductor devices

Device comprising a field-effect transistor in a silicon-on-insulator

BOURDELLE KONSTANTIN

Method of fabricating a back-illuminated image sensor

Methods for manufacturing multilayer wafers with trench structures

SYMETRIX CORP

Process for fabricating layered superlattice materials and AB03 type metal oxides without exposure to oxygen at high temperatures

SIEMENS AG

Apparatus and method for minimizing diffusion in stacked capacitors formed on silicon plugs

ASM INC

Semiconductor buffer structures

FERRANT RICHARD

Semiconductor memory having staggered sense amplifiers associated with a local column decoder

SHAHEEN MOHAMAD

Substrate having a charged zone in an insulating buried layer

COMMISSARIAT ENERGIE ATOMIQUE

Method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate

GAUDIN GWELTAZ

Method for transferring a monocrystalline semiconductor layer onto a support substrate

ENDERS GERHARD

Fully depleted SOI device with buried doped layer

GHYSELEN BRUNO

Forming structures that include a relaxed or pseudo-relaxed layer on a substrate