Inventor
JOHNSON GREGORY A
US32 patents
⚠️ This page may combine multiple inventors who share the name “JOHNSON GREGORY A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI LOGIC CORP
14 patentsUS6441419B1Aug 27, 2002
Encapsulated-metal vertical-interdigitated capacitor and damascene method of manufacturing same
LSI LOGIC CORP91 citations96
US6417535B1Jul 9, 2002
Vertical interdigitated metal-insulator-metal capacitor for an integrated circuit
LSI LOGIC CORP68 citations96
US6251740B1Jun 26, 2001
Method of forming and electrically connecting a vertical interdigitated metal-insulator-metal capacitor extending between interconnect layers in an integrated circuit
LSI LOGIC CORP77 citations96
US6261406B1Jul 17, 2001
Confinement device for use in dry etching of substrate surface and method of dry etching a wafer surface
LSI LOGIC CORP64 citations95
US6303899B1Oct 16, 2001
Method and apparatus for scribing a code in an inactive outer clear out area of a semiconductor wafer
LSI LOGIC CORP33 citations92
US6922817B2Jul 26, 2005
System and method for achieving timing closure in fixed placed designs after implementing logic changes
LSI LOGIC CORP32 citations85
US6174407B1Jan 16, 2001
Apparatus and method for detecting an endpoint of an etching process by transmitting infrared light signals through a semiconductor wafer
LSI LOGIC CORP17 citations84
US6852243B2Feb 8, 2005
Confinement device for use in dry etching of substrate surface and method of dry etching a wafer surface
LSI LOGIC CORP12 citations83
US6699766B1Mar 2, 2004
Method of fabricating an integral capacitor and gate transistor having nitride and oxide polish stop layers using chemical mechanical polishing elimination
LSI LOGIC CORP7 citations74
US6288773B2Sep 11, 2001
Method and apparatus for removing residual material from an alignment mark of a semiconductor wafer
LSI LOGIC CORP14 citations74
US6886147B2Apr 26, 2005
Method, system, and product for achieving optimal timing in a data path that includes variable delay lines and coupled endpoints
LSI LOGIC CORP9 citations68
US7148146B1Dec 12, 2006
Method of fabricating an integral capacitor and gate transistor having nitride and oxide polish stop layers using chemical mechanical polishing elimination
LSI LOGIC CORP4 citations63
US7107375B2Sep 12, 2006
Method for improving selection performance by using an arbitration elimination scheme in a SCSI topology
LSI LOGIC CORP3 citations60
US7076577B2Jul 11, 2006
Pipeline SCSI nexus associativity circuit
LSI LOGIC CORP0 citations50
JOHNSON GREGORY A
3 patentsUS8453882B2Jun 4, 2013
Rapid cooling apparatus and method for dispensed beverages
JOHNSON GREGORY A16 citations82
US8331525B2Dec 11, 2012
Characteristic X-ray computed laminography system for home made explosives (HME) detection
JOHNSON GREGORY A2 citations61
US8755483B2Jun 17, 2014
Nuclear fuel
JOHNSON GREGORY A0 citations51
MINNESOTA MINING & MFG
3 patentsUS5247740ASep 28, 1993
Method and apparatus for cutting a keyway in a mill roll
MINNESOTA MINING & MFG15 citations80
US5439435AAug 8, 1995
Method for cutting a keyway in a mill roll
MINNESOTA MINING & MFG1 citations60
US5439335AAug 8, 1995
Apparatus for cutting a keyway in a mill roll
MINNESOTA MINING & MFG4 citations60