Inventor
AARESTAD JAMES
US3 patents
Patents
3 patentsUS10868535B2Dec 15, 2020
Systems and methods for leveraging path delay variations in a circuit and generating error-tolerant bitstrings
STC UNM2 citations68
US10230369B2Mar 12, 2019
Systems and methods for leveraging path delay variations in a circuit and generating error-tolerant bitstrings
STC UNM4 citations68
US10666256B2May 26, 2020
Systems and methods for leveraging path delay variations in a circuit and generating error-tolerant bitstrings
STC UNM0 citations48