Inventor

MOLL LAURENT R

US34 patents

⚠️ This page may combine multiple inventors who share the name “MOLL LAURENT R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MOLL LAURENT R

BROADCOM CORP

Peripheral bus switch having virtual peripheral bus and configurable host bridge

Hypertransport/SPI-4 interface supporting configurable deskewing

Addressing scheme supporting variable local addressing and variable global addressing

System having two or more packet interfaces, a switch, and a shared packet DMA circuit

System having interfaces and switch that separates coherent and packet traffic

Apparatus and method to receive and align incoming data including SPI data in a buffer to expand data width by utilizing a single read port and single write port memory device

Peripheral bus transaction routing using primary and node ID routing information

Apparatus and method to receive and decode incoming data and to handle repeated simultaneous small fragments

Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems

Addressing scheme supporting fixed local addressing and variable global addressing

System having interfaces and switch that separates coherent and packet traffic

Transparent data format within host device supporting differing transaction types

Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems

Systems including packet interfaces, switches, and packet DMA circuits for splitting and merging packet streams

Receiving data from virtual channels

Peripheral bus switch having virtual peripheral bus and configurable host bridge

Systems including packet interfaces, switches, and packet DMA circuits for splitting and merging packet streams

SUN MICROSYSTEMS INC

Re-fetching cache memory enabling low-power modes

Reduced-power memory with per-sector ground control

Prefetch hardware efficiency via prefetch hint instructions

Reduced-power memory with per-sector power/ground control and early address

System and method for optimizing a memory controller

Power conservation via DRAM access reduction

Small and power-efficient cache that can provide data for background DNA devices while the processor is in a low-power state

Cache operations with hierarchy control

ORACLE AMERICA INC

Power conservation via DRAM access

Virtual core management

Re-fetching cache memory enabling alternative operational modes

Re-fetching cache memory having coherent re-fetching

Small and power-efficient cache that can provide data for background DMA devices while the processor is in a low-power state

Power conservation via DRAM access reduction

CHENG YU QING

Virtual core management

Oracle America

System and method for conserving power

MOLL LAURENT R

Hypertransport/SPI-4 interface supporting configurable deskewing