Inventor

PAI DEEPAK K

US28 patents

⚠️ This page may combine multiple inventors who share the name “PAI DEEPAK K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PAI DEEPAK K

GEN DYNAMICS ADVANCED INF SYS

Process for manufacturing laminated high layer count printed circuit boards

System and method of using a compliant lead interposer

Technique for laminating multiple substrates

Laminated multiple substrates

Laminated multilayer package

Apparatus and method for a segmented squeegee for stenciling

Method and apparatus to change solder pad size using a differential pad plating

Method for forming laminated multiple substrates

Method and apparatus for compliantly connecting stack of high-density electronic modules in harsh environments

CERIDIAN CORP

Hermetically sealed circuit modules having conductive cap anchors

Plated compliant lead

Plated compliant lead

Process of measuring coplanarity of circuit pads and/or grid arrays

Mask alignment mark system

Method of fabricating conductive structures on substrates

Method and apparatus to evaluate effectiveness of cleaning systems for high density electronics

Mark of an electronic component lid

GEN DYNAMICS INF SYSTEMS INC

Method of performing an operation on an integrated circuit

Apparatus for performing a function on an integrated circuit

Laminated multilayer substrates

Method and apparatus to compliantly interconnect commercial-off-the-shelf chip scale packages and printed wiring boards

Method and apparatus to compliantly interconnect area grid arrays and printed wiring boards

PAI DEEPAK K

Method of connecting a grid array package to a printed circuit board

Low profile compliant leads

Method for manufacturing leads

CONTROL DATA CORP

Compliant S-leads for chip carriers

Method for cleaning process control

GEN DYNAMICS INFORMATION

Laminated multilayer substrates