Inventor
BREBNER GORDON J
US46 patents
⚠️ This page may combine multiple inventors who share the name “BREBNER GORDON J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
XILINX INC
35 patentsUS7185309B1Feb 27, 2007
Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip
XILINX INC51 citations96
US7574680B1Aug 11, 2009
Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip
XILINX INC35 citations92
US7552042B1Jun 23, 2009
Method for message processing on a programmable logic device
XILINX INC26 citations92
US7281093B1Oct 9, 2007
Memory apparatus for a message processing system and method of providing same
XILINX INC39 citations92
US7228520B1Jun 5, 2007
Method and apparatus for a programmable interface of a soft platform on a programmable logic device
XILINX INC37 citations92
US6891397B1May 10, 2005
Gigabit router on a single programmable logic device
XILINX INC45 citations92
US6794896B1Sep 21, 2004
Method and apparatus for multithreading
XILINX INC47 citations92
US8015386B1Sep 6, 2011
Configurable memory manager
XILINX INC14 citations84
US7770179B1Aug 3, 2010
Method and apparatus for multithreading on a programmable logic device
XILINX INC16 citations84
US7669166B1Feb 23, 2010
Generation of a specification of a processor of network packets
XILINX INC12 citations84
US7636908B1Dec 22, 2009
Generation of a specification of a network packet processor
XILINX INC11 citations84
US7398502B1Jul 8, 2008
Micro-coded processors for concurrent processing in a programmable logic device
XILINX INC13 citations84
US7379451B1May 27, 2008
Address lookup table
XILINX INC18 citations84
US9674081B1Jun 6, 2017
Efficient mapping of table pipelines for software-defined networking (SDN) data plane
XILINX INC7 citations83
US9110524B1Aug 18, 2015
High throughput finite state machine
XILINX INC7 citations82
US7839849B1Nov 23, 2010
Formatting fields of communication packets
XILINX INC7 citations74
US9270517B1Feb 23, 2016
Tuple construction from data packets
XILINX INC4 citations73
US8358653B1Jan 22, 2013
Generating a pipeline of a packet processor from a parsing tree
XILINX INC6 citations73
US7784014B1Aug 24, 2010
Generation of a specification of a network packet processor
XILINX INC7 citations73
US11831743B1Nov 28, 2023
Streaming architecture for packet parsing
XILINX INC3 citations68
US11425036B1Aug 23, 2022
Pipelined match-action circuitry
XILINX INC4 citations68
US10834241B1Nov 10, 2020
Streaming editor circuit for implementing a packet deparsing process
XILINX INC2 citations68
US8385340B1Feb 26, 2013
Pipeline of a packet processor programmed to concurrently perform operations
XILINX INC4 citations63
US7949793B1May 24, 2011
Method and apparatus for providing an interface between a programmable circuit and a processor
XILINX INC2 citations63
US7817657B1Oct 19, 2010
Circuit for processing network packets
XILINX INC5 citations63
US7804844B1Sep 28, 2010
Dataflow pipeline implementing actions for manipulating packets of a communication protocol
XILINX INC2 citations63
US7454587B1Nov 18, 2008
Method and apparatus for memory management in an integrated circuit
XILINX INC4 citations63
US7822066B1Oct 26, 2010
Processing variable size fields of the packets of a communication protocol
XILINX INC5 citations62
US7852117B1Dec 14, 2010
Hierarchical interface for IC system
XILINX INC2 citations59
US11290361B1Mar 29, 2022
Programmable network measurement engine
XILINX INC1 citations58
US11431815B1Aug 30, 2022
Mining proxy acceleration
XILINX INC0 citations48
US9350385B2May 24, 2016
Modular and scalable cyclic redundancy check computation circuit
XILINX INC1 citations48
US7949007B1May 24, 2011
Methods of clustering actions for manipulating packets of a communication protocol
XILINX INC0 citations42
US7949790B1May 24, 2011
Machines for inserting or removing fixed length data at a fixed location in a serial data stream
XILINX INC0 citations42
US7636909B1Dec 22, 2009
Automatically generating multithreaded datapaths
XILINX INC0 citations42
BREBNER GORDON J
5 patentsUS8560996B1Oct 15, 2013
Method and system for preparing modularized circuit designs for dynamic partial reconfiguration of programmable logic
BREBNER GORDON J30 citations90
US8775685B1Jul 8, 2014
Parallel processing of network packets
BREBNER GORDON J17 citations83
US8065130B1Nov 22, 2011
Method for message processing on a programmable logic device
BREBNER GORDON J6 citations73
US8266583B1Sep 11, 2012
Flexible packet data storage for diverse packet processing applications
BREBNER GORDON J2 citations62
US8780914B2Jul 15, 2014
Parallel processing of network packets
BREBNER GORDON J0 citations41
ATTIG MICHAEL E
4 patentsUS8311057B1Nov 13, 2012
Managing formatting of packets of a communication protocol
ATTIG MICHAEL E20 citations83
US8160092B1Apr 17, 2012
Transforming a declarative description of a packet processor
ATTIG MICHAEL E8 citations83
US8443102B1May 14, 2013
Pipeline of a packet processor programmed to extract packet fields
ATTIG MICHAEL E2 citations62
US8144702B1Mar 27, 2012
Generation of a pipeline for processing a type of network packets
ATTIG MICHAEL E4 citations62