Inventor
DREIBELBIS BRIAN
US9 patents
⚠️ This page may combine multiple inventors who share the name “DREIBELBIS BRIAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
8 patentsUS8949765B2Feb 3, 2015
Modeling multi-patterning variability with statistical timing
IBM5 citations84
US8850378B2Sep 30, 2014
Hierarchical design of integrated circuits with multi-patterning requirements
IBM6 citations84
US8839167B1Sep 16, 2014
Reducing runtime and memory requirements of static timing analysis
IBM18 citations84
US8769452B2Jul 1, 2014
Parasitic extraction in an integrated circuit with multi-patterning requirements
IBM7 citations84
US8806402B2Aug 12, 2014
Modeling multi-patterning variability with statistical timing
IBM4 citations73
US9378328B2Jun 28, 2016
Modeling multi-patterning variability with statistical timing
IBM2 citations62
US9348962B2May 24, 2016
Hierarchical design of integrated circuits with multi-patterning requirements
IBM2 citations62
US9171124B2Oct 27, 2015
Parasitic extraction in an integrated circuit with multi-patterning requirements
IBM1 citations52