Inventor

LUI SIK K

US55 patents

⚠️ This page may combine multiple inventors who share the name “LUI SIK K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LUI SIK K

ALPHA & OMEGA SEMICONDUCTOR

Shielded gate trench (SGT) MOSFET cells implemented with a schottky source contact

Trench junction barrier controlled Schottky device with top and bottom doped regions for enhancing forward current in a vertical direction

Shielded gate trench (SGT) MOSFET devices and manufacturing processes

Power semiconductor package

High speed switching MOSFETS using multi-parallel die packages with/without special leadframes

Active clamp protection circuit for power semiconductor device for high frequency switching

Inverted-trench grounded-source FET structure with trenched source body short electrode

Device structure and manufacturing method using HDP deposited source-body implant block

Inverted-trench grounded-source FET structure with trenched source body short electrode

Shielded gate trench (SGT) MOSFET devices and manufacturing processes

MOSFET using gate work function engineering for switching applications

Configurations and method for carrying out wafer level unclamped inductive switching (UIS) tests

Power MOSFET device structure for high frequency applications

Thermally stable semiconductor power device

Integrated circuit package for semiconductor devices having a reduced leadframe pad and an increased bonding area

MOSFET for synchronous rectification

Configurations and method for carrying out wafer level unclamped inductive switching (UIS) tests

MOSFET for synchronous rectification

Low cost power MOSFET with current monitoring

Inverted J-lead for power devices

MOSFET with a second poly and an inter-poly dielectric layer over gate for synchronous rectification

MOSFET for synchronous rectification

Thermally stable semiconductor power device

Calibration technique for measuring gate resistance of power MOS gate device at water level

MOSFET switch circuit for slow switching application

MOSFET with a second poly and an inter-poly dielectric layer over gate for synchronous rectification

BHALLA ANUP

MOSFET using gate work function engineering for switching applications

Power MOS device fabrication

Shielded gate trench (SGT) MOSFET devices and manufacturing processes

Device structure and manufacturing method using HDP deposited source-body implant block

Power MOSFET device structure for high frequency applications

Shielded gate trench (SGT) mosfet devices and manufacturing processes

Device structure and manufacturing method using HDP deposited using deposited source-body implant block

Power MOS device fabrication

Calibration technique for measuring gate resistance of power MOS gate device at wafer level

Power MOSFET device structure for high frequency applications

INTEGRATED DEVICE TECH

Circuits for improving the reliability of antifuses in integrated circuits

Circuits for improving the reliablity of antifuses in integrated circuits

High resolution circuit and method for sensing antifuses

Redundancy circuit for programmable integrated circuits

Redundancy circuit for programmable integrated circuits

LUI SIK K

Robust semiconductor power devices with design to protect transistor cells with slower switching speed

Trench junction barrier controlled Schottky

LUO LEESHAWN

Integrated circuit package for semiconductor devices with improved electric resistance and inductance

Integrated circuit package for semiconductior devices with improved electric resistance and inductance

ALPHS & OMEGA SEMICONDUCTOR LT

Shielded gate trench (SGT) MOSFET cells implemented with a schottky source contact

(unassigned)

Integrated circuit package for semiconductor devices with improved electric resistance and inductance

ALPHA & OMEGA SEMICONDUCTORS L

Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout

BOBDE MADHUR

Edge termination configurations for high voltage semiconductor power devices

SIERRA SEMICONDUCTOR CORP

Method for making bipolar transistor by self-aligning the emitter to the base contact diffusion