Inventor

SMITH RODNEY WAYNE

US68 patents

⚠️ This page may combine multiple inventors who share the name “SMITH RODNEY WAYNE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SMITH RODNEY WAYNE

QUALCOMM INC

Effective use of a BHT in processor having variable length instruction set execution modes

Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor

System and method wherein conditional instructions unconditionally provide output

Link stack repair of erroneous speculative update

System, method and software to preload instructions from an instruction set other than one currently executing

System, method and software to preload instructions from a variable-length instruction set with proper pre-decoding

Segmented pipeline flushing for mispredicted branches

Power efficient instruction prefetch mechanism

Power saving methods and apparatus to selectively enable cache bits based on known processor state

Pre-decode error handling via branch correction

Method and apparatus for efficiently accessing first and second branch history tables to predict branch instructions

Caching memory attribute indicators with cached memory data field

Apparatus for generating return address predictions for implicit and explicit subroutine calls

Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions

Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media

System and method for using a working global history register

Pre-decoding variable length instructions

Method and apparatus for prefetching non-sequential instruction addresses

Sliding-window, block-based branch target address cache

Caching instructions for a multiple-state processor

Handling cache miss in an instruction crossing a cache line boundary

Conditional instruction execution via emissary instruction for condition evaluation

Method and apparatus for managing a return stack

Virtually-tagged instruction cache with physically-tagged behavior

Use of register renaming system for forwarding intermediate results between constituent instructions of an expanded instruction

Method and apparatus for managing cache partitioning using a dynamic boundary

Method, apparatus, and system for reducing live readiness calculations in reservation stations

Method and system for expanding a conditional instruction into a unconditional instruction and a select instruction

Debug circuit comparing processor instruction set operating mode

Optimizing performance for context-dependent instructions

Efficient interrupt return address save mechanism

MICROSOFT TECHNOLOGY LICENSING LLC

Recovering register mapping state of a flushed instruction employing a snapshot of another register mapping state and traversing reorder buffer (ROB) entries in a processor

Performing flush recovery using parallel walks of sliced reorder buffers (SROBs)

Minimizing traversal of a processor reorder buffer (ROB) for register rename map table (RMT) state recovery for interrupted instruction recovery in a processor

Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions

Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions

Systems and methods for processing instructions having wide immediate operands

Operand-based reach explicit dataflow processors, and related methods and computer-readable media

IBM

System and method for tracing program execution within a superscalar processor

Speculative instruction issue in a simultaneously multithreaded processor

Efficiently calculating a branch target address

Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructions

Translation look aside buffer (TLB) with increased translational capacity for multi-threaded computer processes

DIEFFENDERFER JAMES NORRIS

Link stack repair of erroneous speculative update

Link stack repair of erroneous speculative update

SARTORIUS THOMAS ANDREW

Power efficient instruction prefetch mechanism

Preloading instructions from an instruction set other than a currently executing instruction set

SMITH RODNEY WAYNE

Methods and system for resolving simultaneous predicted branch instructions

Predecode repair cache for instructions that cross an instruction cache line

STEMPEL BRIAN MICHAEL

Method and apparatus for generating return address predictions for implicit and explicit subroutine calls using predecode information