Inventor

DIEFFENDERFER JAMES NORRIS

US93 patents

⚠️ This page may combine multiple inventors who share the name “DIEFFENDERFER JAMES NORRIS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DIEFFENDERFER JAMES NORRIS

QUALCOMM INC

System and method of correcting a branch misprediction

Data prefetch throttle

System and method wherein conditional instructions unconditionally provide output

Link stack repair of erroneous speculative update

Segmented pipeline flushing for mispredicted branches

Power efficient instruction prefetch mechanism

TLB lock indicator

Power saving methods and apparatus to selectively enable cache bits based on known processor state

Pre-decode error handling via branch correction

Method and system for optimizing translation lookaside buffer entries

Method and apparatus for efficiently accessing first and second branch history tables to predict branch instructions

Caching memory attribute indicators with cached memory data field

Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system

Apparatus for generating return address predictions for implicit and explicit subroutine calls

Methods and apparatus for predicting unaligned memory access

Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions

Method and apparatus for segregating shared and non-shared data in cache memory banks

Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media

Apparatus and methods to reduce castouts in a multi-level cache hierarchy

Methods and apparatus for issuing memory barrier commands in a weakly ordered storage system

System and method for using a working global history register

Method and apparatus for managing instruction flushing in a microprocessor&#39;s instruction pipeline

Sliding-window, block-based branch target address cache

Method and system for providing an energy efficient register file

Global modified indicator to reduce power consumption on cache miss

Power saving methods and apparatus to selectively enable comparators in a CAM renaming register file based on known processor state

Conditional instruction execution via emissary instruction for condition evaluation

Method and apparatus for managing a return stack

IBM

Reducing power in a snooping cache based multiprocessor environment

Memory defect steering circuit

Delay-locked loop which includes a monitor to allow for proper alignment of signals

Re-ordering a first request within a FIFO request queue to a different queue position when the first request receives a retry response from the target

System on a chip bus with automatic pipeline stage insertion for timing closure

Ensuring orderly forward progress in granting snoop castout requests

Random access memory having an adaptable latency

Systems and arrangements for promoting a line to exclusive in a fill buffer of a cache

Method and system for providing a reusable configurable self-test controller for manufactured integrated circuits

Method for moving snoop pushes to the front of a request queue

Multiprocessor environment supporting variable-sized coherency transactions

DIEFFENDERFER JAMES NORRIS

Representing loop branches in a branch history register with multiple bits

Link stack repair of erroneous speculative update

Early conditional selection of an operand

Method and a system for accelerating procedure return sequences

MICROSOFT TECHNOLOGY LICENSING LLC

Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions

Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions

SPEIER THOMAS PHILIP

Apparatus and methods to reduce castouts in a multi-level cache hierarchy

HOFMANN RICHARD GERARD

Enforcing strongly-ordered requests in a weakly-ordered processing

STEMPEL BRIAN MICHAEL

Method and apparatus for generating return address predictions for implicit and explicit subroutine calls using predecode information

KOTHARI KULIN N

Multi level indirect predictor using confidence counter and program counter address filter scheme

PANAVICH JASON LAWRENCE

Auto-ordering of strongly ordered, device, and exclusive transactions across multiple memory regions

Method and apparatus for managing instruction flushing in a microprocessor's instruction pipeline