Inventor

MCILVAINE MICHAEL SCOTT

US51 patents

⚠️ This page may combine multiple inventors who share the name “MCILVAINE MICHAEL SCOTT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MCILVAINE MICHAEL SCOTT

QUALCOMM INC

System and method of correcting a branch misprediction

System and method wherein conditional instructions unconditionally provide output

Segmented pipeline flushing for mispredicted branches

Power efficient instruction prefetch mechanism

Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media

Method and apparatus for managing instruction flushing in a microprocessor&#39;s instruction pipeline

Method and system for providing an energy efficient register file

Power saving methods and apparatus to selectively enable comparators in a CAM renaming register file based on known processor state

Conditional instruction execution via emissary instruction for condition evaluation

Dynamic pipeline throttling using confidence-based weighting of in-flight branch instructions

Use of register renaming system for forwarding intermediate results between constituent instructions of an expanded instruction

Method and system for expanding a conditional instruction into a unconditional instruction and a select instruction

Optimizing performance for context-dependent instructions

Efficient interrupt return address save mechanism

Eliminating redundant masking operations instruction processing circuits, and related processor systems, methods, and computer-readable media

Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce execution pipeline bubbles, and related systems, methods, and computer-readable media

Dependency-prediction of instructions

Method and apparatus for cache tag compression

Method to improve speed of executing return branch instructions in a processor

Fusing conditional write instructions having opposite conditions in instruction processing circuits, and related processor systems, methods, and computer-readable media

Precise invalidation of virtually tagged caches

Methods and apparatus for managing page crossing instructions with different cacheability

Branch prediction based on load-path history

MICROSOFT TECHNOLOGY LICENSING LLC

Swapping and restoring context-specific branch predictor states on context switches in a processor

Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions

Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions

Reusing fetched, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-fetching

Reusing fetched, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-fetching

Reusing executed, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-execution

Operand-based reach explicit dataflow processors, and related methods and computer-readable media

Accelerating fetch target queue (FTQ) processing in a processor

Methods and circuitry for efficient management of local branch history registers

Methods and circuitry for efficient management of local branch history registers

Processor branch prediction circuit employing back-invalidation of prediction cache entries based on decoded branch instructions and related methods

Load instruction with final read indicator field to invalidate a buffer or cache entry storing the memory address holding load data

Performing branch predictor training using probabilistic counter updates in a processor

Reach-based explicit dataflow processors, and related computer-readable media and methods

Providing exception stack management using stack panic fault exceptions in processor-based devices

Cache management circuits for predictive adjustment of cache control policies based on persistent, history-based cache control information

Selectively updating branch predictors for loops executed from loop buffers in a processor

Providing extended branch target buffer (BTB) entries for storing trunk branch metadata and leaf branch metadata

Delivering immediate values by using program counter (PC)-relative load instructions to fetch literal data in processor-based devices

BURDA GREGORY CHRISTOPHER

Write-through-read (WTR) comparator circuits, systems, and methods use of same with a multiple-port file

IBM

Speculative instruction issue in a simultaneously multithreaded processor

KOTHARI KULIN N

Multi level indirect predictor using confidence counter and program counter address filter scheme

DIEFFENDERFER JAMES NORRIS

Early conditional selection of an operand

SARTORIUS THOMAS ANDREW

Power efficient instruction prefetch mechanism

DEBRUYNE LESLIE MARK

Method and apparatus for tracking extra data permissions in an instruction cache

KLEIN ANTHONY D

Register-based shifts for a unidirectional rotator

SETH KIRAN RAVI

System and method for executing instructions prior to an execution stage in a processor

Method and apparatus for managing instruction flushing in a microprocessor's instruction pipeline