Inventor

SARTORIUS THOMAS ANDREW

US94 patents

⚠️ This page may combine multiple inventors who share the name “SARTORIUS THOMAS ANDREW”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SARTORIUS THOMAS ANDREW

IBM

Address pipelining for data transfers

System and method for tracing program execution within a processor before and after a triggering event

System and method for tracing program instructions before and after a trace triggering event within a processor

Methods and architectures for overlapped read and write operations

Dynamic control of power management circuitry

System and method for program execution tracing within an integrated processor

System and method for tracing program execution within a superscalar processor

Reducing power in a snooping cache based multiprocessor environment

Systems and methods for dynamically controlling a bus

Method and apparatus for processing null terminated character strings

Speculative instruction issue in a simultaneously multithreaded processor

Re-ordering a first request within a FIFO request queue to a different queue position when the first request receives a retry response from the target

System on a chip bus with automatic pipeline stage insertion for timing closure

Multiple frequency communications

Methods and apparatus for control of speculative memory accesses

Method and apparatus for efficiently providing data from a data storage medium to a processing entity

Ensuring orderly forward progress in granting snoop castout requests

Efficiently calculating a branch target address

Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructions

Methods, cache memories, systems and computer program products for storing transient, normal, and locked entries in an associative cache memory

Method for moving snoop pushes to the front of a request queue

QUALCOMM INC

System and method of correcting a branch misprediction

System and method wherein conditional instructions unconditionally provide output

System, method and software to preload instructions from an instruction set other than one currently executing

System, method and software to preload instructions from a variable-length instruction set with proper pre-decoding

Segmented pipeline flushing for mispredicted branches

Power efficient instruction prefetch mechanism

TLB lock indicator

Power saving methods and apparatus to selectively enable cache bits based on known processor state

Pre-decode error handling via branch correction

Method and system for optimizing translation lookaside buffer entries

Method and apparatus for efficiently accessing first and second branch history tables to predict branch instructions

Method and apparatus to save and restore system memory management unit (MMU) contexts

Apparatus for generating return address predictions for implicit and explicit subroutine calls

Methods and apparatus for predicting unaligned memory access

Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions

Externally programmable memory management unit

Systems and methods of executing multiple hypervisors using multiple sets of processors

Apparatus and methods to reduce castouts in a multi-level cache hierarchy

Methods and apparatus for issuing memory barrier commands in a weakly ordered storage system

System and method for using a working global history register

MICROSOFT TECHNOLOGY LICENSING LLC

Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions

Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions

SPEIER THOMAS PHILIP

Apparatus and methods to reduce castouts in a multi-level cache hierarchy

HOFMANN RICHARD GERARD

Enforcing strongly-ordered requests in a weakly-ordered processing

STEMPEL BRIAN MICHAEL

Method and apparatus for generating return address predictions for implicit and explicit subroutine calls using predecode information

DIEFFENDERFER JAMES NORRIS

Early conditional selection of an operand

SHARP COLIN CHRISTOPHER

Multiple sets of attribute fields within a single page table entry

RYCHLIK BOHUSLAV

Memory management unit with pre-filling capability

PANAVICH JASON LAWRENCE

Auto-ordering of strongly ordered, device, and exclusive transactions across multiple memory regions