Inventor
COORAY NIRANJAN L
US29 patents
⚠️ This page may combine multiple inventors who share the name “COORAY NIRANJAN L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
26 patentsUS6216215B1Apr 10, 2001
Method and apparatus for senior loads
INTEL CORP95 citations97
US6202129B1Mar 13, 2001
Shared cache structure for temporal and non-temporal information using indicative bits
INTEL CORP94 citations97
US6122715ASep 19, 2000
Method and system for optimizing write combining performance in a shared buffer structure
INTEL CORP84 citations96
US6643745B1Nov 4, 2003
Method and apparatus for prefetching data into cache
INTEL CORP93 citations95
US10380039B2Aug 13, 2019
Apparatus and method for memory management in a graphics processing environment
INTEL CORP17 citations94
US6584547B2Jun 24, 2003
Shared cache structure for temporal and non-temporal instructions
INTEL CORP26 citations92
US6526499B2Feb 25, 2003
Method and apparatus for load buffers
INTEL CORP17 citations92
US10891773B2Jan 12, 2021
Apparatus and method for efficient graphics virtualization
INTEL CORP8 citations84
US11360914B2Jun 14, 2022
Apparatus and method for memory management in a graphics processing environment
INTEL CORP1 citations73
US10769078B2Sep 8, 2020
Apparatus and method for memory management in a graphics processing environment
INTEL CORP1 citations73
US10802970B1Oct 13, 2020
Control surface access using flat memory mapping
INTEL CORP2 citations72
US9582432B2Feb 28, 2017
Instruction and logic for support of code modification in translation lookaside buffers
INTEL CORP2 citations72
US10249017B2Apr 2, 2019
Apparatus and method for shared resource partitioning through credit management
INTEL CORP2 citations68
US11080213B2Aug 3, 2021
Apparatus and method for dynamic provisioning, quality of service, and scheduling in a graphics processor
INTEL CORP0 citations63
US10303594B2May 28, 2019
Guaranteed forward progress mechanism
INTEL CORP1 citations63
US11475623B2Oct 18, 2022
Apparatus and method for efficient graphics virtualization
INTEL CORP0 citations62
US11416402B2Aug 16, 2022
Control surface access using flat memory mapping
INTEL CORP0 citations62
US9009413B2Apr 14, 2015
Method and apparatus to implement lazy flush in a virtually tagged cache memory
INTEL CORP2 citations60
US11023998B2Jun 1, 2021
Apparatus and method for shared resource partitioning through credit management
INTEL CORP0 citations58
US11321262B2May 3, 2022
Interconnected systems fence mechanism
INTEL CORP0 citations52
US10860468B2Dec 8, 2020
Guaranteed forward progress mechanism
INTEL CORP0 citations52
US10496563B2Dec 3, 2019
Apparatus and method for dynamic provisioning, quality of service, and scheduling in a graphics processor
INTEL CORP0 citations52
US10599582B2Mar 24, 2020
Using a virtual to virtual address table for memory compression
INTEL CORP0 citations51
US9367477B2Jun 14, 2016
Instruction and logic for support of code modification in translation lookaside buffers
INTEL CORP1 citations51
US7124277B2Oct 17, 2006
Method and apparatus for a trace cache trace-end predictor
INTEL CORP1 citations48
US10372621B2Aug 6, 2019
Mechanism to support variable size page translations
INTEL CORP0 citations47