Inventor

MAJUMDAR AMLAN

US124 patents

⚠️ This page may combine multiple inventors who share the name “MAJUMDAR AMLAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MAJUMDAR AMLAN

IBM

Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts

Embedded DRAM integrated circuits with extremely thin silicon-on-insulator pass transistors

Extremely-thin silicon-on-insulator transistor with raised source/drain

III-V nanowire FET with compositionally-graded channel and wide-bandgap core

III-V finFETs on silicon substrate

Back-gated fully depleted SOI transistor

Ultra-thin SOI CMOS with raised epitaxial source and drain and embedded SiGe PFET extension

Extremely-thin silicon-on-insulator transistor with raised source/drain

Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels

Graded buffer epitaxy in aspect ratio trapping

Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts

Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels

Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels

Nanowire field effect transistor with inner and outer gates

Fabrication process for mitigating external resistance and interface state density in a multigate device

Complementary metal-oxide-semiconductor structure with III-V and silicon germanium transistors on insulator

Low interfacial defect field effect transistor

Nanowire capacitor for bidirectional operation

III-V device with overlapped extension regions using replacement gate

Wire-last integration method and structure for III-V nanowire devices

Partially depleted SOI field effect transistor having a metallized source side halo region

Partially depleted SOI field effect transistor having a metallized source side halo region

Metal-gated MOSFET devices having scaled gate stack thickness including gettering species in a buried oxide

INTEL CORP

Carbon nanotube energy well (CNEW) field effect transistor

Block contact architectures for nanoscale channel transistors

Methods for patterning a semiconductor film

Method of ion implanting for tri-gate devices

Block contact architectures for nanoscale channel transistors

Method for fabricating transistor with thinned channel

Semiconductor device structures and methods of forming semiconductor structures

Semiconductor device structures and methods of forming semiconductor structures

Fabrication of channel wraparound gate structure for field-effect transistor

Mechanism for forming a remote delta doping layer of a quantum well structure

Transistor for non volatile memory devices having a carbon nanotube channel and electrically floating quantum dots in its gate dielectric

Transistor for non volatile memory devices having a carbon nanotube channel and electrically floating quantum dots in its gate dielectric

BRASK JUSTIN K

Semiconductor device structures and methods of forming semiconductor structures

Method for fabricating transistor with thinned channel

Semiconductor device structures and methods of forming semiconductor structures

BANGSARUNTIP SARUNYA

Nanowire circuits in matched devices

Nanowire tunnel field effect transistors

LAUER ISAAC

Fabrication of a vertical heterojunction tunnel-FET

Fabrication of a vertical heterojunction tunnel-FET

MAJUMDAR AMLAN

Semiconductor device having localized extremely thin silicon on insulator channel region

Stressed source/drain CMOS and method for forming same

CHANG JOSEPHINE B

Replacement spacer for tunnel FETs

CHEN KANGGUO

Method to form low series resistance transistor devices on silicon on insulator layer

GLOBALFOUNDRIES INC

Multiple via structure and method

CAI JIN

Method for fabricating super-steep retrograde well MOSFET on SOI or bulk silicon substrate, and device fabricated in accordance with the method

ADAM THOMAS N

Semiconductor structure having NFET extension last implants

CHENG KANGGUO

Semiconductor structure having NFET extension last implants