Inventor

DRASNY GABOR

US25 patents

⚠️ This page may combine multiple inventors who share the name “DRASNY GABOR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DRASNY GABOR

IBM

Circuit design evaluation with compact multi-waveform representations

Clock-gating phase algebra for clock analysis

Conditional phase algebra for clock analysis

Circuit design analyzer

Phase algebra for analysis of hierarchical designs

Phase algebra for analysis of hierarchical designs

Phase algebra for analysis of hierarchical designs

Static checking of asynchronous clock domain crossings

Method and apparatus for encoding binary data as a zero terminated string

Clock-gating phase algebra for clock analysis

Unrolling hardware design generate statements in a source window debugger

Circuit design analyzer

Phase algebra for virtual clock and mode extraction in hierarchical designs

Conditional phase algebra for clock analysis

Glitch-aware phase algebra for clock analysis

Clock-gating phase algebra for clock analysis

Phase algebra for virtual clock and mode extraction in hierarchical designs

Glitch-aware phase algebra for clock analysis

Methods for static checking of asynchronous clock domain crossings

Synthesizing VHDL multiple wait FSMS into RT level FSMS by preprocessing

Method, system, and program product for pre-compile processing of hardware design language (HDL) source files

Phase algebra for specifying clocks and modes in hierarchical designs

DRASNY GABOR

Techniques for modeling variables in subprograms of hardware description language programs

Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs by preprocessing

CARBONE RICHARD L H

Compiler option consistency checking during incremental hardware design language compilation