Inventor

MCARDLE TIMOTHY J

US33 patents

⚠️ This page may combine multiple inventors who share the name “MCARDLE TIMOTHY J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MCARDLE TIMOTHY J

GLOBALFOUNDRIES INC

Self-aligned sacrificial epitaxial capping for trench silicide

Epitaxially grown silicon germanium channel FinFET with silicon underlayer

Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming same

Post gate silicon germanium channel condensation and method for producing the same

Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming same

Recess liner for silicon germanium fin formation

Methods, apparatus and system for forming increased surface regions within EPI structures for improved trench silicide

Faceted epitaxial source/drain regions

Graphene transistor with a sublithographic channel width

Self-aligned sacrificial epitaxial capping for trench silicide

Recess liner for silicon germanium fin formation

Buffer layer for modulating Vt across devices

Uniform junction formation in FinFETs

Formation of a graphene layer on a large substrate

Field-effect transistors with a grown silicon-germanium channel

Post gate silicon germanium channel condensation and method for producing the same

Strain retention semiconductor member for channel SiGe layer of pFET

FinFETs with strained channels and reduced on state resistance

Methods of modulating the morphology of epitaxial semiconductor material

Methods of forming a gate-to-source/drain contact structure

IBM

Semiconductor structure and circuit including ordered arrangement of graphene nanoribbons, and methods of forming same

Single crystal source-drain merged by polycrystalline material

Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels

Carbon nanostructure device fabrication utilizing protect layers

Method for forming semiconductor chip with graphene based devices in an interconnect structure of the chip

Carbon nanostructure device fabrication utilizing protect layers

Uniform junction formation in FinFETs

Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels

Semiconductor structure and circuit including ordered arrangement of graphene nanoribbons, and methods of forming same

DIMITRAKOPOULOS CHRISTOS D

Semiconductor chip with graphene based devices in an interconnect structure of the chip

Graphene-containing semiconductor structures and devices on a silicon carbide substrate having a defined miscut angle

CHU JACK O

Graphene growth on a non-hexagonal lattice

Formation of a graphene layer on a large substrate