Inventor

HUNSAKER MIKAL C

US56 patents

⚠️ This page may combine multiple inventors who share the name “HUNSAKER MIKAL C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HUNSAKER MIKAL C

INTEL CORP

Physical write packets processing when posted write error queue is full, with posted write error queue storing physical write requests when posted write packet fails

Starvation prevention scheme for a fixed priority PCI-Express arbiter with grant counters using arbitration pools

Bus interface unit for reflecting state information for a transfer request to a requesting device

Bus interface unit for reflecting state information for a transfer request to a requesting device

Method/apparatus for flushing DMA transmit packet in FIFO when self-ID code generated by counter after bus reset is different than FIFO message self-ID field

Starvation prevention scheme for a fixed priority PCE-express arbiter with grant counters using arbitration pools

Transaction layer link down handling for PCI express

Device for spatially and temporally reordering for data between a processor, memory and peripherals

Method and system for using a patch module to process non-posted request cycles and to control completions returned to requesting device

Issuing requests to a fabric

Apparatus and method for accepting physical write package when the posted write error queue is full

Techniques for inter-component communication based on a state of a chip select pin

Inter-component communication including posted and non-posted transactions

Inter-component communication including slave component initiated transaction

Method and apparatus for processing serial data using a single receive fifo

Rate control of flow control updates

Method and apparatus to reduce idle link power in a platform

Providing multiple decode options for a system-on-chip (SoC) fabric

Apparatus to reduce idle link power in a platform

Dual bus standard switching bus controller

Method, apparatus and system for single-ended communication of transaction layer packets

Data bridge and bridging

Providing a sideband message interface for system on a chip (SoC)

Dynamic delayed transaction buffer configuration based on bus frequency

Platform environment control interface tunneling via enhanced serial peripheral interface

Method and apparatus to reduce idle link power in a platform

Inter-component communication using an interface including master and slave communication

Autodetection of a PCI express device operating at a wireless RF mitigation frequency

Inband messaging method for integrated type-C universal serial bus detection using enhanced serial peripheral interconnect

Method, apparatus and system for maintaining transaction coherecy in a multiple data bus platform

Debug data communication system for multiple chips

Method, apparatus, and system for power management on a CPU die via clock request messaging protocol

Sending packets with expanded headers

Supporting multiple channels of a single interface

Providing error handling support to legacy devices

Common idle state, active state and credit management for an interface

Issuing requests to a fabric

Techniques for inter-component communication based on a state of a chip select pin

LAKSHMANAMURTHY SRIDHAR

Providing error handling support to legacy devices

Common idle state, active state and credit management for an interface

Supporting multiple channels of a single interface

Providing multiple decode options for a system-on-chip (SoC) fabric

Sending packets with expanded headers

Issuing requests to a fabric

Aggregating completion messages in a sideband interface

DIEFENBAUGH PAUL S

Method and apparatus to reduce idle link power in a platform

HUNSAKER MIKAL C

Apparatuses for inter-component communication including slave component initiated transaction

ADLER ROBERT P

Providing a sideband message interface for system on a chip (SoC)

COMPAQ COMPUTER CORP

Memory accessing system with portions of memory being selectively write protectable and relocatable based on predefined register bits and memory selection RAM outputs

BOCK ANTHONY S

Measuring time offsets between devices with independent silicon clocks