Inventor
CHANG KUAN-LUN
TW12 patents
⚠️ This page may combine multiple inventors who share the name “CHANG KUAN-LUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG
6 patentsUS7317221B2Jan 8, 2008
High density MIM capacitor structure and fabrication process
TAIWAN SEMICONDUCTOR MFG29 citations91
US7015086B2Mar 21, 2006
Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology
TAIWAN SEMICONDUCTOR MFG10 citations72
US7238969B2Jul 3, 2007
Semiconductor layout structure for ESD protection circuits
TAIWAN SEMICONDUCTOR MFG4 citations62
US7372102B2May 13, 2008
Structure having a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology
TAIWAN SEMICONDUCTOR MFG3 citations61
US7250344B2Jul 31, 2007
Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology
TAIWAN SEMICONDUCTOR MFG0 citations50
US6847061B2Jan 25, 2005
Elimination of implant damage during manufacture of HBT
TAIWAN SEMICONDUCTOR MFG0 citations48
IND TECH RES INST
5 patentsUS5814547ASep 29, 1998
Forming different depth trenches simultaneously by microloading effect
IND TECH RES INST76 citations95
US6303419B1Oct 16, 2001
Method for fabricating a BiCMOS device featuring twin wells and an N type epitaxial layer
IND TECH RES INST22 citations92
US6352901B1Mar 5, 2002
Method of fabricating a bipolar junction transistor using multiple selectively implanted collector regions
IND TECH RES INST21 citations91
US5656525AAug 12, 1997
Method of manufacturing high aspect-ratio field emitters for flat panel displays
IND TECH RES INST46 citations88
US5869380AFeb 9, 1999
Method for forming a bipolar junction transistor
IND TECH RES INST18 citations83