Inventor

RAHMAN ARIFUR

US101 patents

⚠️ This page may combine multiple inventors who share the name “RAHMAN ARIFUR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAHMAN ARIFUR

XILINX INC

Apparatus for interconnecting stacked dice on a programmable integrated circuit

Integrated circuit with through-die via interface for die stacking

On-chip programmable optical crossbar switch

Linear voltage regulator with dynamically selectable drivers

Hardware stack structure using programmable logic

Circuit for and method of enabling partial reconfiguration of a device having programmable logic

Methods for implementing programmable memory controller for distributed DRAM system-in-package (SiP)

Configuration interface to stacked FPGA

Software model for a hybrid stacked field programmable gate array

Method of forming stacked-die integrated circuit

Semiconductor device having structures for reducing substrate noise coupled from through die vias

Method and apparatus for integrating capacitors in stacked integrated circuits

Low cost bumping and bonding method for stacked die

Methods and apparatus for implementing a stacked memory programmable integrated circuit system in package

Implementation of low power standby modes for integrated circuits

Structures and methods for heterogeneous low power programmable logic device

Writeable shift register lookup table in FPGA with SRAM memory cells in lookup table reprogrammed by writing after initial configuration

Level-shifting pass gate multiplexer

Semiconductor device with through substrate vias

Method and apparatus for integrating capacitors in stacked integrated circuits

RAHMAN ARIFUR

Apparatus and method for testing of stacked die structure

Integrated circuit package with redundant micro-bumps

Apparatus and methodology for testing stacked die

Integrated circuit structure with inductor in silicon interposer

Method and apparatus for programmable heterogeneous integration of stacked semiconductor die

Method and apparatus for programmable device testing in stacked die applications

Method and apparatus for monitoring through-silicon vias

Stress-aware design for integrated circuits comprising a stress inducing structure and keep out zone

Testing die-to-die bonding and rework

Method and apparatus for integrated circuit package thermo-mechanical reliability analysis

Integrated circuit with through-die via interface for die stacking and cross-track routing

Method and apparatus for implementing spatially programmable through die vias in an integrated circuit

ALTERA CORP

Integrated circuits with backside power delivery

Interposer with programmable power gating granularity

2.5D electronic package

Power line layout in integrated circuits

Scalable architecture for IP block integration

Methods and apparatus for controlling interface circuitry

Scalable 2.5D interface circuitry

LATTICE SEMICONDUCTOR CORP

Programmable interface circuit for differential and single-ended signals

Low voltage differential signaling systems and methods

Electronic circuit with on-chip programmable terminations

Programmable common mode termination for input/output circuits

IBM

Three dimensional integrated circuit and method of design

Three dimensional integrated circuit

UNIV POLYTECHNIC

Floating gate field effect transistors for chemical and/or biological sensing

POLITECHNIC INST UNIV NEW YORK

Floating gate field effect transistors for chemical and/or biological sensing

CHANDRASEKAR KARTHIK

Multi-chip packages with reduced power distribution network noise

NGAI TONY

Integrated circuit package with inter-die thermal spreader layers

TUAN TIM

Programmable integrated circuit with voltage domains