Inventor
SHARANGPANI HARSH
US6 patents
Patents
6 patentsUS6408386B1Jun 18, 2002
Method and apparatus for providing event handling functionality in a computer system
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US5774686AJun 30, 1998
Method and apparatus for providing two system architectures in a processor
INTEL CORP104 citations97
US6219774B1Apr 17, 2001
Address translation with/bypassing intermediate segmentation translation to accommodate two different instruction set architecture
INTEL CORP48 citations95
US6560696B1May 6, 2003
Return register stack target predictor
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US6584558B2Jun 24, 2003
Article for providing event handling functionality in a processor supporting different instruction sets
INTEL CORP10 citations73
US7152153B2Dec 19, 2006
Bi-directional return register stack recovery from speculative execution of call/return upon branch misprediction
INTEL CORP4 citations61