Inventor

GAIDE BRIAN C

US59 patents

⚠️ This page may combine multiple inventors who share the name “GAIDE BRIAN C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GAIDE BRIAN C

XILINX INC

Adaptive integrated programmable device platform

Adaptive integrated programmable device platform

Distributed multi-die routing in a multi-chip module

Methods of pipelining a data path in an integrated circuit

Output structure with cascaded control signals for logic blocks in integrated circuits, and methods of using the same

Compute-centric architecture for integrated circuits

Gating logic circuits in a self-timed integrated circuit

Circuits for sharing self-timed logic

Implementing conditional statements in self-timed logic circuits

Adaptive low skew clocking architecture

Register circuits and methods of storing data in a register circuit

Self-timed single track circuit

Circuits for replicating self-timed logic

Multi-mode circuit in a self-timed integrated circuit

Circuits for fanning out data in a programmable self-timed integrated circuit

Circuits for enabling feedback paths in a self-timed integrated circuit

Bus-based logic blocks for self-timed integrated circuits

Dynamically controlled output multiplexer circuits in a programmable integrated circuit

Merging data streams in a self-timed programmable integrated circuit

Selection circuit with programmable constant output

Global clock and a leaf clock divider

Clock network architecture

Selectively providing clock signals using a programmable control circuit

Interconnect multiplexers and methods of reducing contention currents in an interconnect multiplexer

Clock tree routing in a chip stack

Power delivery network for active-on-active stacked integrated circuits

Multi-chip stacked devices

Redundancy scheme for a 3D stacked device

Lut cascading circuit

Circuits for and methods of generating clock signals enabling the latching of data in an integrated circuit

Cascaded LUT carry logic circuit

Programmable interconnect network

Programmable pipeline interface circuit

Programmable power reduction technique using transistor threshold drops

Circuits for and methods of controlling power within an integrated circuit

Programmable termination circuits for programmable devices

Adding soft logic to flush a pipeline and reduce current ramp

Yield recovery scheme for memory

Compute dataflow architecture

Compute dataflow architecture

Redundancy scheme for multi-chip stacked devices

Adaptive integrated programmable device platform

Adaptive integrated programmable device platform

Circuits for and methods of asychronously transmitting data in an integrated circuit

System and method for secure deconstruction sensor in a heterogeneous integration circuitry

YOUNG STEVEN P

Signed multiplier circuit utilizing a uniform array of logic blocks

Circuits for shifting bussed data

Multiplier architecture utilizing a uniform array of logic blocks, and methods of using the same

LU WEIGUANG

Configuration of a multi-die integrated circuit

RAHMAN ARIFUR

Method and apparatus for programmable device testing in stacked die applications