Inventor

SPROGIS EDMUND J

US83 patents

⚠️ This page may combine multiple inventors who share the name “SPROGIS EDMUND J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SPROGIS EDMUND J

IBM

Physically highly secure multi-chip assembly

Dual chip with heat sink

CMOS imager array with recessed dielectric

Physically highly secure multi-chip assembly

Conductive through via process for electronic device carriers

Stacked chip process carrier

Power distribution design method for stacked flip-chip packages

Method of assembling a plurality of semiconductor devices having different thickness

Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage

Semiconductor defect monitor for diagnosing processing-induced defects

Single twist layout and method for paired line conductors of integrated circuits

3D integrated DC-DC power converters

Stacked imager package

Techniques for providing decoupling capacitance

Stacked imager package

Power distribution design method for stacked flip-chip packages

Hybrid open folded sense amplifier architecture for a memory device

Method of manufacture of silicon based package and devices manufactured thereby

Dual chip stack method for electro-static discharge protection of integrated circuits

Low impedance power distribution structure for a semiconductor chip package

On-chip DC-DC power converters with fully integrated GaN power switches, silicon CMOS transistors and magnetic inductors

Integrated decoupling capacitor employing conductive through-substrate vias

Heat sink for integrated circuit devices

Silicon based package

Chip-in-slot interconnect for 3D chip stacks

Hermetic seal and reliable bonding structures for 3D applications

Silicon-on-insulator structures for through via in silicon carriers

Techniques for providing decoupling capacitance

Method of thinning a semiconductor substrate

Method of thinning a semiconductor substrate

Method and apparatus for filling vias

Techniques for providing decoupling capacitance

Techniques for providing decoupling capacitance

Techniques for providing decoupling capacitance

Method for thinning wafers that have contact bumps

Integrated semiconductor device having co-planar device surfaces

Probe for localized neural optogenetics stimulation and neurochemistry recordings

Integrated DC-DC power converters through face-to-face bonding

Stacked chip process carrier

COOLBAUGH DOUGLAS D

Method of making heat sink for integrated circuit devices

Method of cooling a resistor

ANDRY PAUL S

Process for wet singulation using a dicing singulation structure

High-yield method of exposing and contacting through-silicon vias

ANDERSON BRENT A

Silicon-on-insulator structures for through via in silicon carriers

Semiconductor devices having tensile and/or compressive stress and methods of manufacturing

KIM TAE HONG

Integrated decoupling capacitor employing conductive through-substrate vias

GLOBALFOUNDRIES INC

Flattened substrate surface for substrate bonding

MAGERLEIN JOHN H

Method and manufacture of silicon based package and devices manufactured thereby

WEN HUAJUN

Processor voltage regulation

COONEY III EDWARD C

Flattened substrate surface for substrate bonding