Inventor
TSANG CORNELIA K
US54 patents
⚠️ This page may combine multiple inventors who share the name “TSANG CORNELIA K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
34 patentsUS7488680B2Feb 10, 2009
Conductive through via process for electronic device carriers
IBM87 citations98
US7276787B2Oct 2, 2007
Silicon chip carrier with conductive through-vias and method for fabricating same
IBM124 citations96
US7435627B2Oct 14, 2008
Techniques for providing decoupling capacitance
IBM18 citations93
US7741226B2Jun 22, 2010
Optimal tungsten through wafer via and process of fabricating same
IBM31 citations90
US9324601B1Apr 26, 2016
Low temperature adhesive resins for wafer bonding
IBM8 citations84
US8012796B2Sep 6, 2011
Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers
IBM11 citations84
US7799613B2Sep 21, 2010
Integrated module for data processing system
IBM10 citations84
US7683478B2Mar 23, 2010
Hermetic seal and reliable bonding structures for 3D applications
IBM9 citations84
US7645701B2Jan 12, 2010
Silicon-on-insulator structures for through via in silicon carriers
IBM15 citations84
US7488624B2Feb 10, 2009
Techniques for providing decoupling capacitance
IBM9 citations84
US9648782B2May 9, 2017
Chip stack structures that implement two-phase cooling with radial flow
IBM5 citations83
US9472789B2Oct 18, 2016
Thin, flexible microsystem with integrated energy source
IBM9 citations83
US9313921B2Apr 12, 2016
Chip stack structures that implement two-phase cooling with radial flow
IBM12 citations83
US7902069B2Mar 8, 2011
Small area, robust silicon via structure and process
IBM6 citations74
US7791168B2Sep 7, 2010
Techniques for providing decoupling capacitance
IBM6 citations74
US7741231B2Jun 22, 2010
Techniques for providing decoupling capacitance
IBM4 citations74
US7691669B2Apr 6, 2010
Techniques for providing decoupling capacitance
IBM7 citations74
US6815813B1Nov 9, 2004
Self-contained heat sink and a method for fabricating same
IBM10 citations74
US9795964B2Oct 24, 2017
Direct bond transfer layers for manufacturable sealing of microfluidic chips
IBM4 citations73
US9748131B2Aug 29, 2017
Low temperature adhesive resins for wafer bonding
IBM2 citations73
US9362223B2Jun 7, 2016
Integrated circuit assembly with cushion polymer layer
IBM4 citations70
US11127715B2Sep 21, 2021
Large channel interconnects with through silicon Vias (TSVs) and method for constructing the same
IBM0 citations63
US10177116B2Jan 8, 2019
Large channel interconnects with through silicon vias (TSVs) and method for constructing the same
IBM1 citations63
US9601364B2Mar 21, 2017
Low temperature adhesive resins for wafer bonding
IBM1 citations63
US8354737B2Jan 15, 2013
Small area, robust silicon via structure and process
IBM2 citations63
US7786596B2Aug 31, 2010
Hermetic seal and reliable bonding structures for 3D applications
IBM3 citations63
US7282391B1Oct 16, 2007
Method for precision assembly of integrated circuit chip packages
IBM5 citations62
US9941250B2Apr 10, 2018
Chip stack structures that implement two-phase cooling with radial flow
IBM1 citations61
US10625257B2Apr 21, 2020
Direct bond transfer layers for manufacturable sealing of microfluidic chips
IBM0 citations52
US10347588B2Jul 9, 2019
Thin 3D die with electromagnetic radiation blocking encapsulation
IBM0 citations52
US10056337B2Aug 21, 2018
Thin 3D die with electromagnetic radiation blocking encapsulation
IBM0 citations52
US9331141B2May 3, 2016
CMOS structure on replacement substrate
IBM0 citations52
US8927087B2Jan 6, 2015
Bonding of substrates including metal-dielectric patterns with metal raised above dielectric and structures so formed
IBM0 citations52
US7820521B2Oct 26, 2010
Conductive through via structure and process for electronic device carriers
IBM1 citations52
ANDRY PAUL S
9 patentsUS9159602B2Oct 13, 2015
Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers
ANDRY PAUL S14 citations93
US8487425B2Jul 16, 2013
Optimized annular copper TSV
ANDRY PAUL S9 citations84
US8298917B2Oct 30, 2012
Process for wet singulation using a dicing singulation structure
ANDRY PAUL S9 citations84
US8263497B2Sep 11, 2012
High-yield method of exposing and contacting through-silicon vias
ANDRY PAUL S11 citations84
US8592932B2Nov 26, 2013
Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers
ANDRY PAUL S4 citations63
US8440544B2May 14, 2013
CMOS structure and method of manufacture
ANDRY PAUL S4 citations63
US8080876B2Dec 20, 2011
Structure and method for creating reliable deep via connections in a silicon carrier
ANDRY PAUL S2 citations63
US8564113B2Oct 22, 2013
Electrostatic chucking of an insulator handle substrate
ANDRY PAUL S0 citations52
US8242591B2Aug 14, 2012
Electrostatic chucking of an insulator handle substrate
ANDRY PAUL S0 citations52
CHEN KUAN-NENG
2 patentsUS8617689B2Dec 31, 2013
Bonding of substrates including metal-dielectric patterns with metal raised above dielectric and structures so formed
CHEN KUAN-NENG10 citations84
US8241995B2Aug 14, 2012
Bonding of substrates including metal-dielectric patterns with metal raised above dielectric
CHEN KUAN-NENG7 citations84
DANG BING
2 patentsGLOBALFOUNDRIES INC
1 patentANDERSON BRENT A
1 patentCOONEY III EDWARD C
1 patentShowing the top 50 of 54 patents by PatentIndex Score.