Inventor

WORDEMAN MATTHEW R

US47 patents

⚠️ This page may combine multiple inventors who share the name “WORDEMAN MATTHEW R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WORDEMAN MATTHEW R

IBM

Common source transistor capacitor stack

SOI/bulk hybrid substrate and method of forming the same

Charge pump system having multiple charging rates and corresponding method

Charge pump system having multiple independently activated charge pumps and corresponding method

SOI/bulk hybrid substrate and method of forming the same

Pillar CMOS structure

Folder Bitline DRAM having access transistors stacked above trench storage capacitors, each such transistor employing a planar semiconductor body which spans adjacent capacitors

Folded bitline, ultra-high density dynamic random access memory having access transistors stacked above trench storage capacitors

Super low-power generator system for embedded applications

Optical proximity correction method and system

Non-volatile DRAM cell

Three-terminal cascade switch for controlling static power consumption in integrated circuits

Planarized and fill biased integrated circuit chip

Integrated circuit planarization and fill biasing design method

High performance gain cell architecture

Clock system for an embedded semiconductor memory unit

System and method for preventing noise cross contamination between embedded DRAM and system chip

High performance CMOS word-line driver

Method of forming a non-volatile DRAM cell

Trimming MRAM sense amp with offset cancellation

Hermetic seal and reliable bonding structures for 3D applications

3D inter-stratum connectivity robustness

Programmable via structure for three dimensional integration technology

Differential and hierarchical sensing for memory circuits

Pillar CMOS structure

Data output drivers with pull-up devices

Structure for collection of ionization-induced excess minority carriers in a semiconductor substrate and method for the fabrication thereof

STT MRAM midpoint reference cell allowing full write

Command multiplier for built-in-self-test

Hermetic seal and reliable bonding structures for 3D applications

Programmable via structure for three dimensional integration technology

Three-terminal cascade switch for controlling static power consumption in integrated circuits

Differential and hierarchical sensing for memory circuits

Differential and hierarchical sensing for memory circuits

3D integrated circuit stack-wide synchronization circuit

Method for forming pillar CMOS

Method and structure for enabling a redundancy allocation during a multi-bank operation

Dynamic redundancy for memory

KRUSIN-ELBAUM LIA

Three-terminal cascade switch for controlling static power consumption in integrated circuits

Three-terminal cascade switch for controlling static power consumption in integrated circuits

Three-terminal cascade switch for controlling static power consumption in integrated circuits

CHANG LELAND

Adaptive interconnect structure

Method of forming adaptive interconnect structure having programmable contacts

PANG LIANG-TECK

Programming the behavior of individual chips or strata in a 3D stack of integrated circuits

Programming the behavior of individual chips or strata in a 3D stack of integrated circuits

SCHEUERMANN MICHAEL R

Configuration of connections in a 3D stack of integrated circuits

SILBERMAN JOEL A

3D integrated circuit stack-wide synchronization circuit