P

Inventor

YOUNG ALBERT M

US45 patents
⚠️ This page may combine multiple inventors who share the name “YOUNG ALBERT M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

29 patents
US7913202B2Mar 22, 2011

Wafer level I/O test, repair and/or customization enabled by I/O layer

IBM22 citations92
US7521950B2Apr 21, 2009

Wafer level I/O test and repair enabled by I/O layer

IBM21 citations92
US7683478B2Mar 23, 2010

Hermetic seal and reliable bonding structures for 3D applications

IBM9 citations84
US12268031B2Apr 1, 2025

Backside power rails and power distribution network for density scaling

IBM2 citations74
US7545667B2Jun 9, 2009

Programmable via structure for three dimensional integration technology

IBM6 citations74
US12543554B2Feb 3, 2026

Stacked field effect transistor contacts

IBM0 citations63
US12490465B2Dec 2, 2025

Stacked field effect transistor

IBM0 citations63
US12484265B2Nov 25, 2025

Subtractive source drain contact for stacked devices

IBM0 citations63
US12477819B2Nov 18, 2025

Stacked FET with extremely small cell height

IBM0 citations63
US12446320B2Oct 14, 2025

Bottom contact with self-aligned spacer for stacked semiconductor devices

IBM0 citations63
US12424591B2Sep 23, 2025

Method and structure of forming independent contact for staggered CFET

IBM0 citations63
US12322652B2Jun 3, 2025

Local interconnect for cross coupling

IBM0 citations63
US12310072B2May 20, 2025

Middle of line structure with stacked devices

IBM0 citations63
US12278184B2Apr 15, 2025

Vertically-stacked field effect transistor cell

IBM0 citations63
US12136655B2Nov 5, 2024

Backside electrical contacts to buried power rails

IBM0 citations63
US11915966B2Feb 27, 2024

Backside power rail integration

IBM0 citations63
US7786596B2Aug 31, 2010

Hermetic seal and reliable bonding structures for 3D applications

IBM3 citations63
US7732798B2Jun 8, 2010

Programmable via structure for three dimensional integration technology

IBM4 citations63
US7652278B2Jan 26, 2010

Programmable via structure and method of fabricating same

IBM3 citations63
US7528056B2May 5, 2009

Low-cost strained SOI substrate for high-performance CMOS technology

IBM5 citations63
US11956939B2Apr 9, 2024

Static random access memory using vertical transport field effect transistors

IBM0 citations62
US11678475B2Jun 13, 2023

Static random access memory using vertical transport field effect transistors

IBM0 citations62
US7999377B2Aug 16, 2011

Method and structure for optimizing yield of 3-D chip manufacture

IBM2 citations60
US7737003B2Jun 15, 2010

Method and structure for optimizing yield of 3-D chip manufacture

IBM4 citations60
US9887623B2Feb 6, 2018

Efficient voltage conversion

IBM0 citations52
US9755506B2Sep 5, 2017

Efficient voltage conversion

IBM0 citations52
US7888164B2Feb 15, 2011

Programmable via structure and method of fabricating same

IBM0 citations52
US12268026B2Apr 1, 2025

High aspect ratio contact structure with multiple metal stacks

IBM0 citations51
US12142656B2Nov 12, 2024

Staggered stacked semiconductor devices

IBM0 citations47

AEROSPACE CORP

5 patents

FAROOQ MUKTA G

5 patents

MASSACHUSETTS INST TECHNOLOGY

2 patents

CHANG LELAND

2 patents

LIU FEI

1 patent

HARPER JAMES DOUGLAS

1 patent