Inventor
HSU CHIN-HSIUNG
TW28 patents
⚠️ This page may combine multiple inventors who share the name “HSU CHIN-HSIUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG CO LTD
11 patentsUS9262570B2Feb 16, 2016
Layout boundary method
TAIWAN SEMICONDUCTOR MFG CO LTD26 citations94
US9380709B2Jun 28, 2016
Method of cutting conductive patterns
TAIWAN SEMICONDUCTOR MFG CO LTD5 citations84
US9087170B2Jul 21, 2015
Cell layout design and method
TAIWAN SEMICONDUCTOR MFG CO LTD8 citations84
US9563731B2Feb 7, 2017
Cell boundaries for self aligned multiple patterning abutments
TAIWAN SEMICONDUCTOR MFG CO LTD4 citations73
US12013643B2Jun 18, 2024
Method of cutting conductive patterns
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US11429028B2Aug 30, 2022
Method of cutting conductive patterns
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US9223924B2Dec 29, 2015
Method and system for multi-patterning layout decomposition
TAIWAN SEMICONDUCTOR MFG CO LTD2 citations60
US10509322B2Dec 17, 2019
Method of cutting conductive patterns
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
US9384307B2Jul 5, 2016
Stitch and trim methods for double patterning compliant standard cell design
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations52
US9262577B2Feb 16, 2016
Layout method and system for multi-patterning integrated circuits
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
US9026953B2May 5, 2015
Compression method and system for use with multi-patterning
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations52
TAIWAN SEMICONDUCTOR MFG
7 patentsUS8914755B1Dec 16, 2014
Layout re-decomposition for multiple patterning layouts
TAIWAN SEMICONDUCTOR MFG7 citations84
US8813016B1Aug 19, 2014
Multiple via connections using connectivity rings
TAIWAN SEMICONDUCTOR MFG15 citations84
US8799834B1Aug 5, 2014
Self-aligned multiple patterning layout design
TAIWAN SEMICONDUCTOR MFG15 citations83
US8959466B1Feb 17, 2015
Systems and methods for designing layouts for semiconductor device fabrication
TAIWAN SEMICONDUCTOR MFG6 citations73
US9213795B2Dec 15, 2015
Multiple via connections using connectivity rings
TAIWAN SEMICONDUCTOR MFG3 citations63
US8875067B2Oct 28, 2014
Reusable cut mask for multiple layers
TAIWAN SEMICONDUCTOR MFG2 citations63
US8972910B1Mar 3, 2015
Routing method
TAIWAN SEMICONDUCTOR MFG0 citations42
MEDIATEK INC
5 patentsUS9940422B2Apr 10, 2018
Methods for reducing congestion region in layout area of IC
MEDIATEK INC1 citations51
US10162927B2Dec 25, 2018
Methods for redistributing cell densities in layout area of IC
MEDIATEK INC0 citations48
US9946829B2Apr 17, 2018
Methods for redistributing cell densities in layout area of IC
MEDIATEK INC0 citations48
US9892226B2Feb 13, 2018
Methods for providing macro placement of IC
MEDIATEK INC1 citations45
US9817936B2Nov 14, 2017
Methods for minimizing layout area of IC
MEDIATEK INC0 citations40