Inventor

HO HERBERT L

US89 patents

⚠️ This page may combine multiple inventors who share the name “HO HERBERT L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HO HERBERT L

IBM

STI formation in semiconductor device including SOI and bulk silicon regions

Structure and method for producing low leakage isolation devices

Shallow trench isolation with thin nitride liner

Structure and method of fabricating high-density trench-based non-volatile random access SONOS memory cells for SOC applications

Trench metal-insulator-metal (MIM) capacitors integrated with middle-of-line metal contacts, and method of fabricating same

Methods involving silicon-on-insulator trench memory with implanted plate

Trench metal-insulator-metal (MIM) capacitors and method of fabricating same

Low-cost deep trench decoupling capacitor device and process of manufacture

Backside buried strap for SOI DRAM trench capacitor

Method of making backside buried strap for SOI DRAM trench capacitor

Vertical SOI trench SONOS cell

Deep trench capacitor in a SOI substrate having a laterally protruding buried strap

Deep trench capacitor through SOI substrate and methods of forming

Vertical SOI trench SONOS cell

Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof

Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation

Method of forming a trench capacitor DRAM cell

Self-aligned deep trench isolation to shallow trench isolation

Method of making epitaxial cobalt silicide using a thin metal underlayer

Deep trench body SOI contacts with epitaxial layer formation

SOI trench capacitor cell incorporating a low-leakage floating body array transistor

Reliable low resistance strap for trench storage DRAM cell using selective epitaxy

Work function engineering for eDRAM MOSFETs

Simplified buried plate structure and process for semiconductor-on-insulator chip

Deep trench capacitor and method

Trench metal-insulator metal (MIM) capacitors

Collarless trench DRAM device

Copper vias in low-k technology

Method of fabricating a vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness

Process to lower strap, wordline and bitline contact resistance in trench-based DRAMS by silicidization

Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation

Method for determining cell body and biasing plate contact locations for embedded dram in SOI

SOI deep trench capacitor employing a non-conformal inner spacer

Providing isolation for wordline passing over deep trench capacitor

Low resistance strap for high density trench DRAMS

Semiconductor-on-insulator (SOI) deep trench capacitor

Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof

SIEMENS AG

Buried-strap formation in a dram trench capacitor

Three-dimensional device layout with sub-groundrule features

Buried strap formation in a DRAM trench capacitor

Three-dimensional device layout having a trench capacitor

GLOBALFOUNDRIES INC

Deep trench capacitor with metal plate

Non-volatile memory device employing a deep trench capacitor

Changing effective work function using ion implantation during dual work function metal gate integration

TOSHIBA KK

Controlled recrystallization of buried strap in a semiconductor memory device

Controlled recrystallization of buried strap in a semiconductor memory device

ANDERSON BRENT A

Integrated circuit and a method using integrated process steps to form deep trench isolation structures and deep trench capacitor structures for the integrated circuit

Integrated circuit and a method using integrated process steps to form deep trench isolation structures and deep trench capacitor structures for the integrated circuit

CHEN XIANGDONG

Work function engineering for eDRAM MOSFETs

HO HERBERT L

High-density, trench-based non-volatile random access SONOS memory SOC applications