Inventor

SHERAW CHRISTOPHER D

US24 patents

⚠️ This page may combine multiple inventors who share the name “SHERAW CHRISTOPHER D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHERAW CHRISTOPHER D

IBM

Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof

Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation

Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels

Method of fabricating a vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness

Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation

Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof

Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels

Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices

Method of reducing stacking faults through annealing

Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof

Stacking fault reduction in epitaxially grown silicon

Copper contact via structure using hybrid barrier layer

Semiconductor structures including multiple crystallographic orientations and methods for fabrication thereof

CMOS circuits including a passive element having a low end resistance

Structure for improved diode ideality

Stacking fault reduction in epitaxially grown silicon

Decoder for a stationary switch machine

CMOS circuits including a passive element having a low end resistance

GLOBALFOUNDRIES INC

Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming same

Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming same

Conformal buffer layer in source and drain regions of fin-type transistors

Methods of modulating the morphology of epitaxial semiconductor material

BABICH KATHERINA E

Filling narrow openings using ion beam etch

GLOBALFOUNDRIES US INC

Additional spacer for self-aligned contact for only high voltage FinFETs