Inventor
YIP SHERMAN H
US23 patents
⚠️ This page may combine multiple inventors who share the name “YIP SHERMAN H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SUN MICROSYSTEMS INC
10 patentsUS7617421B2Nov 10, 2009
Method and apparatus for reporting failure conditions during transactional execution
SUN MICROSYSTEMS INC60 citations98
US7461208B1Dec 2, 2008
Circuitry and method for accessing an associative cache with parallel determination of data and data availability
SUN MICROSYSTEMS INC78 citations98
US7480787B1Jan 20, 2009
Method and structure for pipelining of SIMD conditional moves
SUN MICROSYSTEMS INC39 citations92
US7331039B1Feb 12, 2008
Method for graphically displaying hardware performance simulators
SUN MICROSYSTEMS INC20 citations92
US7293163B2Nov 6, 2007
Method and apparatus for dynamically adjusting the aggressiveness of an execute-ahead processor to hide memory latency
SUN MICROSYSTEMS INC25 citations92
US7650487B2Jan 19, 2010
Method and structure for coordinating instruction execution in out-of-order processor execution using an instruction including an artificial register dependency
SUN MICROSYSTEMS INC3 citations63
US7610474B2Oct 27, 2009
Mechanism for hardware tracking of return address after tail call elimination of return-type instruction
SUN MICROSYSTEMS INC5 citations63
US7418581B2Aug 26, 2008
Method and apparatus for sampling instructions on a processor that supports speculative execution
SUN MICROSYSTEMS INC4 citations63
US7257700B2Aug 14, 2007
Avoiding register RAW hazards when returning from speculative execution
SUN MICROSYSTEMS INC2 citations63
US7634639B2Dec 15, 2009
Avoiding live-lock in a processor that supports speculative execution
SUN MICROSYSTEMS INC3 citations60
ORACLE AMERICA INC
4 patentsUS8041900B2Oct 18, 2011
Method and apparatus for improving transactional memory commit latency
ORACLE AMERICA INC63 citations98
US8364900B2Jan 29, 2013
Pseudo-LRU cache line replacement for a high-speed cache
ORACLE AMERICA INC4 citations63
US7757068B2Jul 13, 2010
Method and apparatus for measuring performance during speculative execution
ORACLE AMERICA INC3 citations63
US7716457B2May 11, 2010
Method and apparatus for counting instructions during speculative execution
ORACLE AMERICA INC2 citations63
YIP SHERMAN H
3 patentsUS8181002B1May 15, 2012
Merging checkpoints in an execute-ahead processor
YIP SHERMAN H2 citations60
US8572356B2Oct 29, 2013
Space-efficient mechanism to support additional scouting in a processor using checkpoints
YIP SHERMAN H0 citations49
US8316366B2Nov 20, 2012
Facilitating transactional execution in a processor that supports simultaneous speculative threading
YIP SHERMAN H0 citations39