Inventor

SENGOKU SHOICHIRO

US55 patents

⚠️ This page may combine multiple inventors who share the name “SENGOKU SHOICHIRO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SENGOKU SHOICHIRO

QUALCOMM INC

N-factorial voltage mode driver

Camera control interface extension with in-band interrupt

Method and apparatus to enable multiple masters to operate in a single master bus architecture

Clock and data recovery for pulse based multi-wire link

I3C high data rate (HDR) always-on image sensor 8-bit operation indicator and buffer over threshold indicator

Method to enhance MIPI D-PHY link rate with minimal PHY changes and no protocol changes

Methods to send extra information in-band on inter-integrated circuit (I2C) bus

Camera control interface extension bus

Multi-wire single-ended push-pull link with data symbol transition based clocking

Circuit to recover a clock signal from multiple wire data signals that changes state every state cycle and is immune to data inter-lane skew as well as data state transition glitches

Transcoding method for multi-wire signaling that embeds clock information in transition of signal state

Compact and fast N-factorial single data rate clock and data recovery circuits

Multi-lane N-factorial (N!) and other multi-wire communication systems

N factorial dual data rate clock and data recovery

Multi-wire single-ended push-pull link with data symbol transition based clocking

Efficient N-factorial differential signaling termination network

Error detection constants of symbol transition clocking transcoding

Methods to send extra information in-band on inter-integrated circuit (I2C) bus

In-band interrupt time stamp

Multi-wire symbol transition clocking symbol error correction

Multi-lane N-factorial (N!) and other multi-wire communication systems

Receive clock calibration for a serial bus

Multi-wire open-drain link with data symbol transition based clocking

Camera control interface extension bus

Multi-wire open-drain link with data symbol transition based clocking

Method for using error correction codes with N factorial or CCI extension

Clock and data recovery for pulse based multi-wire link

Sharing hardware resources between D-PHY and N-factorial termination networks

Clock and data recovery for pulse based multi-wire link

Farewell reset and restart method for coexistence of legacy and next generation devices over a shared multi-mode bus

CCIe receiver logic register write only with receiver clock

Camera control interface slave device to slave device communication

Coexistence of legacy and next generation devices over a shared multi-mode bus

Method to enhance MIPI D-PHY link rate with minimal PHY changes and no protocol changes

Transcoding and transmission over a serial bus

Actuator ring characteristic measurement method

Camera control slave devices with multiple slave device identifiers

Error detection capability over CCIe protocol

System and methods for damping lens ringing

Transcoding method for multi-wire signaling that embeds clock information in transition of signal state

Slave identifier scanning and hot-plug capability over CCIe bus

Multi-lane N-factorial (N!) and other multi-wire communication systems

Camera control interface extension bus

Method and apparatus to enable multiple masters to operate in a single master bus architecture

NEC CORP

Test access port controller with a gate for controlling a shift data register signal

Method and apparatus for controlling clock signal period

Semiconductor device capable of carrying out high speed fault detecting test

APPLE INC

Methods and apparatus for streaming media conversion with reduced buffering memories

Modified Manchester encoding for ultra-low power interfaces

Accurate period measurement and synchronization through sensor stream interface