Inventor

AINSPAN HERSCHEL A

US29 patents

⚠️ This page may combine multiple inventors who share the name “AINSPAN HERSCHEL A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AINSPAN HERSCHEL A

IBM

Dual-mode non-return-to-zero (NRZ)/ four-level pulse amplitude modulation (PAM4) receiver with digitally enhanced NRZ sensitivity

Phase-locked loop circuits and methods implementing multiplexer circuit for fine tuning control of digitally controlled oscillators

Adjusting the magnitude of a capacitance of a digitally controlled circuit

Removing deterministic phase errors from fractional-N PLLS

Prediction based digital control for fractional-N PLLs

Minimum-spacing circuit design and layout for PICA

Phase-locked loop circuits and methods implementing pulsewidth modulation for fine tuning control of digitally controlled oscillators

Phase-locked loop using continuously auto-tuned inductor-capacitor voltage controlled oscillator

Scalable polarimetric phased array transceiver

Transmitter with fully re-assignable segments for reconfigurable FFE taps

Adjusting the magnitude of a capacitance of a digitally controlled circuit

Scalable polarimetric phased array transceiver

Scalable polarimetric phased array transceiver

Adjusting the magnitude of a capacitance of a digitally controlled circuit

Prediction based digital control for fractional-N PLLs

Structure for an inductor-capacitor voltage-controlled oscillator

Differential current switch to super buffer logic level translator

Minimum-spacing circuit design and layout for PICA

Removing deterministic phase errors from fractional-N PLLs

Compensating for process variation in integrated circuit fabrication

Variable-gain-amplifier based limiter to remove amplitude modulation from a VCO output

AINSPAN HERSCHEL A

Ultra-compact PLL with wide tuning range and low noise

Hybrid phase-locked loop architectures

Ultra-compact PLL with wide tuning range and low noise

Optimal dithering of a digitally controlled oscillator with clock dithering for gain and bandwidth control

Hybrid phase-locked loop architectures

Minimum-spacing circuit design and layout for PICA

Varactor tuning control using redundant numbering

GLOBALFOUNDRIES INC

Structure for an inductor-capacitor voltage-controlled oscillator