Inventor
WELTERLEN BENOÎT
FR3 patents
⚠️ This page may combine multiple inventors who share the name “WELTERLEN BENOÎT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
BULL SAS
2 patentsUS10838768B2Nov 17, 2020
Method for optimizing memory access in a microprocessor including several logic cores upon resumption of executing an application, and computer implementing such a method
BULL SAS0 citations46
US10491564B2Nov 26, 2019
Process for assigning a network address to a terminal network-element, network, interconnection network-element, addressing server and associated terminal network-element
BULL SAS0 citations28