Inventor

FANNING BLAISE

US71 patents

⚠️ This page may combine multiple inventors who share the name “FANNING BLAISE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FANNING BLAISE

INTEL CORP

General input/output architecture, protocol and related methods to implement flow control

General input/output architecture, protocol and related methods to manage data integrity

General input/output architecture with PCI express protocol with credit-based flow control

General input/output architecture, protocol and related methods to implement flow control

General input/output architecture, protocol and related methods to implement flow control

General input/output architecture, protocol and related methods to implement flow control

General input/output architecture, protocol and related methods to implement flow control

Detecting and handling bus errors in a computer system

General input/output architecture, protocol and related methods to manage data integrity

Multi-level memory with direct access

General input/output architecture, protocol and related methods to implement flow control

Techniques to configure a solid state drive to operate in a storage mode or a memory mode

Issuing requests to a fabric

General input/output architecture, protocol and related methods to implement flow control

Remapping memory devices during operation

Hybrid exclusive multi-level memory architecture with memory management

Adaptive configuration of non-volatile memory

General input/output architecture, protocol and related methods to implement flow control

Techniques to configure a solid state drive to operate in a storage mode or a memory mode

Providing multiple decode options for a system-on-chip (SoC) fabric

Arbitrating memory accesses via a shared memory fabric

Apparatus and method for shared least recently used (LRU) policy between multiple cache levels

Isochronous agent data pinning in a multi-level memory system

Multi-level memory with direct access

General input/output architecture, protocol and related methods to implement flow control

Multi-level memory with direct access

Providing a sideband message interface for system on a chip (SoC)

Techniques to configure a solid state drive to operate in a storage mode or a memory mode

Method and apparatus for pinning memory pages in a multi-level system memory

Multi-level memory with direct access

Memory latency management

LAKSHMANAMURTHY SRIDHAR

Providing error handling support to legacy devices

Common idle state, active state and credit management for an interface

Providing multiple decode options for a system-on-chip (SoC) fabric

Supporting multiple channels of a single interface

Sending packets with expanded headers

Issuing requests to a fabric

Aggregating completion messages in a sideband interface

DIGITAL EQUIPMENT CORP

Address method for computer graphics system

Method and apparatus for varying command length in a computer graphics system

Graphics command processing method in a computer graphics system

Translation of virtual addresses in a computer graphics system

FANNING BLAISE

Multi-level memory with direct access

Apparatus and method for managing register information in a processing system

AJANOVIC JASMIN

General input/output architecture, protocol and related methods to implement flow control

PUTHIYEDATH LEENA K

Apparatus for configuring partitions within phase change memory of tablet computer with integrated memory controller emulating mass storage to storage driver based on request from software

ADLER ROBERT P

Providing a sideband message interface for system on a chip (SoC)

CROSSLAND JAMES B

RAM disk using non-volatile random access memory

QAWAMI SHEKOUFEH

Adaptive configuration of non-volatile memory

RACHAKONDA RAMANA

Power mode control method and circuitry