Inventor

CROSSLAND JAMES B

US54 patents

⚠️ This page may combine multiple inventors who share the name “CROSSLAND JAMES B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CROSSLAND JAMES B

INTEL CORP

Mechanism for processor power state aware distribution of lowest priority interrupt

OS and firmware coordinated error handling using transparent firmware intercept and firmware services

Method and apparatus for suspending execution of a thread until a specified memory access occurs

Coherency techniques for suspending execution of a thread until a specified memory access occurs

Queued locks using monitor-memory wait

Hot plug cache coherent interface method and apparatus

Queued locks using monitor-memory wait

Method, system, and apparatus for rerouting interrupts in a multi-core processor

Hot plug interface control method and apparatus

Apparatus and method for enumeration of processors during hot-plug of a compute node

Method and apparatus for functional redundancy check mode recovery

Platform and method for initializing components within hot-plugged nodes

Creation of logical APIC ID with cluster ID and intra-cluster ID

Processor selection for an interrupt based on willingness to accept the interrupt and on priority

Apparatus and method for enumeration of processors during hot-plug of a compute node

Queued locks using monitor-memory wait

Method and apparatus for preventing software side channel attacks

Platform and method for supporting hibernate operations

Linear to physical address translation with support for page attributes

Programmable event driven yield mechanism which may activate service threads

Technique for communicating interrupts in a computer system

Processor selection for an interrupt identifying a processor cluster

Mechanism for processor power state aware distribution of lowest priority interrupts

Systems and methods for preventing unauthorized stack pivoting

Linear to physical address translation with support for page attributes

Linear to physical address translation with support for page attributes

Methods, apparatus, and instructions for user-level thread suspension

Linear to physical address translation with support for page attributes

Methods, apparatus, and instructions for user level thread suspension

Apparatuses and methods for generating a suppressed address trace

Apparatus, system, and method to enable transparent memory hot plug/remove

I/O hub resident cache line monitor and device register update

Apparatuses and methods for generating a suppressed address trace

System for configuring partitions within non-volatile random access memory (NVRAM) as a replacement for traditional mass storage

RAM disk using non-volatile random access memory

TIRUVALLUR KESHAVAN

Technique for communicating interrupts in a computer system

Technique for communicating interrupts in a computer system

PATEL BAIJU V

Managing and implementing metadata in central processing unit using register extensions

Robust and high performance instructions for system call

CONRAD SHAUN M

Apparatus and method for tracking TLB flushes on a per thread basis

NEIGER GILBERT

Detecting spin loops in a virtual machine environment

PUTHIYEDATH LEENA K

Apparatus for configuring partitions within phase change memory of tablet computer with integrated memory controller emulating mass storage to storage driver based on request from software

VARGAS JOSE A

Machine check summary register

SANKARAN RAJESH M

Method and apparatus for TLB shoot-down in a heterogeneous computing system supporting shared virtual memory

HAMMARLUND PER

Inter-processor interrupts

CROSSLAND JAMES B

RAM disk using non-volatile random access memory

VAN DYKE DON A

Context state management for processor feature sets

UNM RAINFOREST INNOVATIONS

Linear to physical address translation with support for page attributes

FALIK OHAD

Linear to physical address translation with support for page attributes

VAN DYKE DON

Context state management for processor feature sets