Inventor

CRADDOCK DAVID F

US79 patents

⚠️ This page may combine multiple inventors who share the name “CRADDOCK DAVID F”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CRADDOCK DAVID F

IBM

End node partitioning using virtualization

Infiniband general services queue pair virtualization for multiple logical ports on a single physical port

Apparatus, system and method for implementing a generalized queue pair in a system area network

Apparatus, system and method for providing multiple logical channel adapters within a single physical channel adapter in a system area network

Infiniband work and completion queue management via head and tail circular buffers with indirect work queue entries

Infiniband multicast operation in an LPAR environment

Apparatus, system and method for controlling access to facilities based on usage classes

Method for pacing buffered data transfers over a network such as fibre channel

Apparatus and method for managing work and completion queues using head and tail pointers

Synchronous input/output using a low latency storage controller connection

Method, apparatus, and computer program product for migrating data pages by disabling selected DMA operations in a physical I/O adapter

Apparatus and method for virtualizing a queue pair space to minimize time-wait impacts

Apparatus and method for swapping-out real memory by inhibiting i/o operations to a memory region and setting a quiescent indicator, responsive to determining the current number of outstanding operations

Sharing memory tables between host channel adapters

Memory mapped input/output emulation

Infiniband memory windows management directly in hardware

Using an access key to protect and point to regions in windows for infiniband

Synchronous input/output diagnostic controls

Synchronous input/output diagnostic controls

Synchronous input/output commands writing to multiple targets

Low latency queue pairs for I/O adapters

Hardware enforcement of logical partitioning of a channel adapter&#39;s resources in a system area network

Infiniband multicast operation in an LPAR environment

Method and apparatus for associating memory windows with memory regions in a data storage system

Apparatus and method for managing work and completion queues using head and tail pointers with end-to-end context error cache for reliable datagram

Synchronous input/output computer system including hardware invalidation of synchronous input/output context

Synchronous data input/output system using prefetched device table entry

Computer system including synchronous input/output and hardware assisted purge of address translation cache entries of synchronous input/output transactions

Synchronous input/output replication of data in a persistent storage control unit

Synchronous input/output initialization exchange sequences

Synchronous input/output initialization exchange sequences

Peripheral device access using synchronous input/output

Peripheral device access using synchronous input/output

Synchronous input/output commands writing to multiple targets

Synchronous input/output command with partial completion

Synchronous input/output using a low latency storage controller connection

Synchronous input/output command with partial completion

Error detection and recovery for synchronous input/output operations

Dynamic universal port mode assignment

Upbound input/output expansion request and response processing in a PCIe architecture

Synchronous input / output hardware acknowledgement of write completions

Synchronous input/output (I/O) cache line padding

Supporting flexible deployment and migration of virtual servers via unique function identifiers

Access control and security for synchronous input/output links

Dynamic universal port mode assignment

GREGG THOMAS A

Input/output (I/O) expansion response processing in a peripheral component interconnect express (PCIe) environment

Upbound input/output expansion request and response processing in a PCIe architecture

CHECK MARK A

Memory error isolation and recovery in a multiprocessor computer system

BAYER GERD K

Switch failover control in a multiprocessor computer system

LAIS ERIC N

System and method for routing I/O expansion requests and responses in a PCIE architecture

Hardware enforcement of logical partitioning of a channel adapter's resources in a system area network