Inventor

SISTLA KRISHNAKANTH V

US82 patents

⚠️ This page may combine multiple inventors who share the name “SISTLA KRISHNAKANTH V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SISTLA KRISHNAKANTH V

INTEL CORP

Controlling telemetry data communication in a processor

Dynamically updating logical identifiers of cores of a processor

Monitor implementation in a multicore processor with inclusive LLC

Home node aware replacement policy for caches in a multiprocessor system

Configuration of base clock frequency of processor based on usage parameters

Method and apparatus to control a link power state

Masking a power state of a core of a processor

Multiple dies hardware processors and methods

Forcing core low power states in a processor

Collaborative processor and system performance and power management

Current control for a multicore processor

User level control of power management policies

Apparatus and method for a user configurable reliability control loop

Collaborative processor and system performance and power management

Performing dynamic power control of platform devices

Adaptively controlling low power mode operation for a cache memory

Managing performance policies based on workload scalability

Configuration of base clock frequency of processor based on usage parameters

Configuration of base clock frequency of processor based on usage parameters

Thread scheduling using processing engine information

Multiple dies hardware processors and methods

Mechanism to provide workload and configuration-aware deterministic performance for microprocessors

Changing the clock frequency of a computing device

Preventing system snoop and cross-snoop conflicts

Efficient usage of last level caches in a MCMP system using application level configuration

Enforcing global ordering through a caching bridge in a multicore multiprocessor system

Configuration of base clock frequency of processor based on usage parameters

Current control for a multicore processor

Current control for a multicore processor

Dynamically updating logical identifiers of cores of a processor

Current control for a multicore processor

Optimizing power usage by factoring processor architectural events to PMU

Computing platform interface with memory management

User level control of power management policies

User level control of power management policies

Multiple dies hardware processors and methods

Apparatus and method to provide a thermal parameter report for a multi-chip package

Multiple dies hardware processors and methods

Hybrid prioritized resource allocation in thermally-or power-constrained computing devices

Apparatus and method to provide a thermal parameter report for a multi-chip package

Hybrid prioritized resource allocation in thermally- or power-constrained computing devices

SISTLA KRISHNAKANTH V

User level control of power management policies

Dynamically modifying a power/performance tradeoff based on processor utilization

Method, apparatus, and system for energy efficiency and energy conservation including dynamic control of energy consumption in power domains

VARMA ANKUSH

Dynamically measuring power consumption in a processor

Mechanism to provide workload and configuration-aware deterministic performance for microprocessors

THERIEN GUY M

Collaborative processor and system performance and power management

Collaborative processor and system performance and power management

RUSU STEFAN

Wear-out equalization techniques for multiple functional units

CAI ZHONG-NING

Cache coherency sequencing implementation and adaptive LLC access priority control for CMP