Inventor

COONEY III EDWARD C

US60 patents

⚠️ This page may combine multiple inventors who share the name “COONEY III EDWARD C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

COONEY III EDWARD C

IBM

Device and methodology for reducing effective dielectric constant in semiconductor devices

Fluorine-free barrier layer between conductor and insulator for degradation prevention

Fluorine barrier layer between conductor and insulator for degradation prevention

Method for providing fluorine barrier layer between conductor and insulator for degradation prevention

Fluorine barrier layer between conductor and insulator for degradation prevention

Device and methodology for reducing effective dielectric constant in semiconductor devices

Exposed pore sealing post patterning

Metal spacer in single and dual damascene processing

Sacrificial metal spacer damascene process

Damascene interconnect structures including etchback for low-k dielectric materials

Process to create robust contacts and interconnects

Ultra-thin tantalum nitride copper interconnect barrier

Single and multilevel rework

Single and multilevel rework

Wafer clamp ring for use in an ionized physical vapor deposition apparatus

Optimal tungsten through wafer via and process of fabricating same

Vertical integrated circuit switches, design structure and methods of fabricating same

Device and methodology for reducing effective dielectric constant in semiconductor devices

Copper alloy via bottom liner

Process for interfacial adhesion in laminate structures through patterned roughing of a surface

Device and methodology for reducing effective dielectric constant in semiconductor devices

Exposed pore sealing post patterning

Sacrificial metal spacer damascene process

Metal spacer in single and dual damascence processing

Metal oxide temperature monitor

Process and apparatus for cold copper deposition to enhance copper plating fill

Semiconductor chip with anti-reverse engineering function

Process for interfacial adhesion in laminate structures through patterned roughing of a surface

Metal spacer in single and dual damascene processing

Method and apparatus for selectively altering dielectric properties of localized semiconductor device regions

Metal seed layer deposition

Metal seed layer deposition

Method of annealing copper metallurgy

Methods of managing metal density in dicing channel and related integrated circuit structures

Imager microlens structure having interfacial region for adhesion of protective layer

Thick on-chip high-performance wiring structures

COONEY III EDWARD C

Structure and method for reducing vertical crack propagation

Flattened substrate surface for substrate bonding

Thick on-chip high-performance wiring structures

Integrated circuit including wire structure, related method and design structure

GLOBALFOUNDRIES INC

Flattened substrate surface for substrate bonding

Laser scribe structures for a wafer

Structure for BEOL metal levels with multiple dielectric layers for improved dielectric to metal adhesion

Integrated circuit including wire structure, related method and design structure

EDELSTEIN DANIEL C

Reducing effective dielectric constant in semiconductor devices

Copper alloy via bottom liner

ANDRY PAUL S

Electrostatic chucking of an insulator handle substrate

Electrostatic chucking of an insulator handle substrate

ANDERSON FELIX P

Vertical integrated circuit switches, design structure and methods of fabricating same

CHRISMAN GREGORY S

Top corner rounding of damascene wire for insulator crack suppression