Inventor

SPEIGHT WILLIAM E

US47 patents

⚠️ This page may combine multiple inventors who share the name “SPEIGHT WILLIAM E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SPEIGHT WILLIAM E

IBM

Performing collective operations using software setup and partial software execution at leaf nodes in a multi-tiered full-graph interconnect architecture

Dynamic adjustment of prefetch stream priority

Branch target address cache

System and method of managing cache hierarchies with adaptive mechanisms

Stackable module for energy-efficient computing systems

Cache directed sequential prefetch

Efficient multiple-table reference prediction mechanism

Complier assisted victim cache bypassing

Dynamically adjusting a pre-fetch distance to enable just-in-time prefetching within a processing system

Fast and accurate proton therapy dose calculations

Providing full hardware support of collective operations in a multi-tiered full-graph interconnect architecture

Routing information through a data processing system implementing a multi-tiered full-graph interconnect architecture

System and method for contention-based cache performance optimization

Techniques for dynamically sharing a fabric to facilitate off-chip communication for multiple on-chip units

Remote asynchronous data mover

Complier assisted victim cache bypassing

ARIMILLI RAVI K

Sourcing differing amounts of prefetch data in response to data prefetch requests

Techniques for indirect data prefetching

Techniques for data prefetching using indirect addressing with offset

Techniques for prediction-based indirect data prefetching

Varying a data prefetch size based upon data usage

Varying an amount of data retrieved from memory based upon an instruction hint

Data prefetching using indirect addressing

Techniques for multi-level indirect data prefetching

ARIMILLI LAKSHMINARAYANA B

Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks

Hardware based dynamic load balancing of message passing interface tasks

Hardware based dynamic load balancing of message passing interface tasks by modifying tasks

Method for data processing using a multi-tiered full-graph interconnect architecture

Modifying an operation of one or more processors executing message passing interface tasks

Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks

System for data processing using a multi-tiered full-graph interconnect architecture

LI JIAN

Read and write aware cache with a read portion and a write portion of a tag and status array

Latency-tolerant 3D on-chip memory organization

Reducing energy consumption of set associative caches by reducing checked ways of the set association

Read and write aware cache storing cache lines in a read-often portion and a write-often portion

Non-uniform cache architecture (NUCA)

SPEIGHT WILLIAM E

Jump starting prefetch streams across page boundaries

Cache directed sequential prefetch

Assigning memory to on-chip coherence domains

Assigning memory to on-chip coherence domains

CARTER JOHN B

Scalable space-optimized and energy-efficient computing system

Instruction set architecture extensions for performing power versus performance tradeoffs

RAJAMONY RAMAKRISHNAN

Fine grained cache allocation

Address translation through an intermediate address space

ELNOZAHY ELMOOTAZBELLAH N

Method and system for performance isolation in virtualized environments

Mechanisms for reducing DRAM power consumption

RANGAN RAM

Techniques for predicated execution in an out-of-order processor