Inventor
TOPALOGLU RASIT O
US44 patents
⚠️ This page may combine multiple inventors who share the name “TOPALOGLU RASIT O”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
36 patentsUS10068184B1Sep 4, 2018
Vertical superconducting capacitors for transmon qubits
IBM43 citations98
US9947660B1Apr 17, 2018
Two dimension material fin sidewall
IBM15 citations92
US10312200B2Jun 4, 2019
Integrated circuit security
IBM5 citations84
US10103144B1Oct 16, 2018
Two dimension material fin sidewall
IBM4 citations84
US10916253B2Feb 9, 2021
Spoken microagreements with blockchain
IBM4 citations73
US10840295B2Nov 17, 2020
Fluxonium qubits and devices including plurality of vertical stacks of Josephson junctions
IBM3 citations73
US10665635B1May 26, 2020
Persistent flux biasing methodology for superconducting loops
IBM5 citations73
US10573606B2Feb 25, 2020
Integrated circuit security
IBM2 citations73
US10559564B2Feb 11, 2020
Two dimension material fin sidewall
IBM1 citations73
US10552758B2Feb 4, 2020
Vertical superconducting capacitors for transmon qubits
IBM1 citations73
US10529908B2Jan 7, 2020
Backside coupling with superconducting partial TSV for transmon qubits
IBM2 citations73
US10446736B2Oct 15, 2019
Backside coupling with superconducting partial TSV for transmon qubits
IBM2 citations73
US10103145B1Oct 16, 2018
Two dimension material fin sidewall
IBM2 citations73
US9859208B1Jan 2, 2018
Bottom self-aligned via
IBM2 citations73
US9837491B2Dec 5, 2017
Stacked carbon nanotube multiple threshold device
IBM3 citations73
US9373538B2Jun 21, 2016
Interconnect level structures for confining stitch-induced via structures
IBM3 citations73
US8806393B1Aug 12, 2014
Generation of design shapes for confining stitch-induced via structures
IBM6 citations73
US10796949B2Oct 6, 2020
Airgap vias in electrical interconnects
IBM2 citations71
US10896883B2Jan 19, 2021
Integrated circuit security
IBM0 citations62
US11011415B2May 18, 2021
Airgap vias in electrical interconnects
IBM0 citations60
US11593470B2Feb 28, 2023
Volumetric display-based CAPTCHA system
IBM0 citations52
US10804454B2Oct 13, 2020
Backside coupling with superconducting partial TSV for transmon qubits
IBM0 citations52
US10445651B2Oct 15, 2019
Vertical superconducting capacitors for transmon qubits
IBM0 citations52
US10169525B2Jan 1, 2019
Multiple-depth trench interconnect technology at advanced semiconductor nodes
IBM0 citations52
US10170474B2Jan 1, 2019
Two dimension material fin sidewall
IBM0 citations52
US10152567B2Dec 11, 2018
Early overlay prediction and overlay-aware mask design
IBM0 citations52
US9940429B2Apr 10, 2018
Early overlay prediction and overlay-aware mask design
IBM0 citations52
US9710592B2Jul 18, 2017
Multiple-depth trench interconnect technology at advanced semiconductor nodes
IBM0 citations52
US9601367B2Mar 21, 2017
Interconnect level structures for confining stitch-induced via structures
IBM0 citations52
US9424388B2Aug 23, 2016
Dividing lithography exposure fields to improve semiconductor fabrication
IBM0 citations52
US11487508B2Nov 1, 2022
Magnetic tunnel junction based true random number generator
IBM0 citations50
US10394992B2Aug 27, 2019
Wire lineend to via overlap optimization
IBM0 citations42
US10142335B2Nov 27, 2018
Dynamic intrinsic chip identification
IBM0 citations42
US9569578B1Feb 14, 2017
Mask decomposition and optimization for directed self assembly
IBM0 citations42
US9454631B2Sep 27, 2016
Stitch-derived via structures and methods of generating the same
IBM0 citations42
US9058457B2Jun 16, 2015
Reticle data decomposition for focal plane determination in lithographic processes
IBM0 citations41
TOPALOGLU RASIT O
3 patentsUS8219994B2Jul 10, 2012
Work balancing scheduler for processor cores and methods thereof
TOPALOGLU RASIT O22 citations91
US8099269B2Jan 17, 2012
Two-step simulation methodology for aging simulations
TOPALOGLU RASIT O15 citations83
US9159711B2Oct 13, 2015
Integrated circuit systems including vertical inductors
TOPALOGLU RASIT O2 citations61