Inventor

THAKKAR SHREEKANT S

US71 patents

Patents

50 patents

US6678825B1Jan 13, 2004

Controlling access to multiple isolated memories in an isolated execution environment

INTEL CORP177 citations99

US6633963B1Oct 14, 2003

Controlling access to multiple memory zones in an isolated execution environment

INTEL CORP220 citations99

US6507904B1Jan 14, 2003

Executing isolated mode instructions in a secure system running in privilege rings

INTEL CORP289 citations99

US7082615B1Jul 25, 2006

Protecting software environment in isolated execution

INTEL CORP78 citations98

US6996710B1Feb 7, 2006

Platform and method for issuing and certifying a hardware-protected attestation key

INTEL CORP74 citations98

US6883019B1Apr 19, 2005

Method and apparatus for parallel conversion of color values from a single precision floating point format to an integer format

INTEL CORP112 citations98

US6292815B1Sep 18, 2001

Data conversion between floating point packed format and integer scalar format

INTEL CORP98 citations97

US6211892B1Apr 3, 2001

System and method for performing an intra-add operation

INTEL CORP98 citations97

US7783819B2Aug 24, 2010

Integrating non-peripheral component interconnect (PCI) resources into a personal computer system

INTEL CORP29 citations96

US7013484B1Mar 14, 2006

Managing a secure environment using a chipset in isolated execution mode

INTEL CORP62 citations96

US6990579B1Jan 24, 2006

Platform and method for remote attestation of a platform

INTEL CORP60 citations96

US6795905B1Sep 21, 2004

Controlling accesses to isolated memory using a memory controller for isolated execution

INTEL CORP58 citations96

US6502115B2Dec 31, 2002

Conversion between packed floating point data and packed 32-bit integer data in different architectural registers

INTEL CORP50 citations96

US6266769B1Jul 24, 2001

Conversion between packed floating point data and packed 32-bit integer data in different architectural registers

INTEL CORP49 citations96

US6263426B1Jul 17, 2001

Conversion from packed floating point data to packed 8-bit integer data in different architectural registers

INTEL CORP55 citations96

US6247116B1Jun 12, 2001

Conversion from packed floating point data to packed 16-bit integer data in different architectural registers

INTEL CORP69 citations96

US6073210AJun 6, 2000

Synchronization of weakly ordered write combining operations using a fencing mechanism

INTEL CORP76 citations96

US6925553B2Aug 2, 2005

Staggering execution of a single packed data instruction using the same circuit

INTEL CORP30 citations95

US6288723B1Sep 11, 2001

Method and apparatus for converting data format to a graphics card

INTEL CORP82 citations95

US6230257B1May 8, 2001

Method and apparatus for staggering execution of a single packed data instruction using the same circuit

INTEL CORP39 citations95

US7155601B2Dec 26, 2006

Multi-element operand sub-portion shuffle instruction execution

INTEL CORP73 citations94

US6317824B1Nov 13, 2001

Method and apparatus for performing integer operations in response to a result of a floating point operation

INTEL CORP85 citations94

US7254707B2Aug 7, 2007

Platform and method for remote attestation of a platform

INTEL CORP20 citations93

US7194634B2Mar 20, 2007

Attestation key memory device and bus

INTEL CORP27 citations93

US7111167B1Sep 19, 2006

Digital watermarks with values derived from remote platforms

INTEL CORP46 citations93

US7096497B2Aug 22, 2006

File checking using remote signing authority via a network

INTEL CORP32 citations93

US7085935B1Aug 1, 2006

Managing a secure environment using a chipset in isolated execution mode

INTEL CORP22 citations93

US7073071B1Jul 4, 2006

Platform and method for generating and utilizing a protected audit log

INTEL CORP19 citations93

US7013481B1Mar 14, 2006

Attestation key memory device and bus

INTEL CORP44 citations93

US6934817B2Aug 23, 2005

Controlling access to multiple memory zones in an isolated execution environment

INTEL CORP44 citations93

US6754815B1Jun 22, 2004

Method and system for scrubbing an isolated area of memory after reset of a processor operating in isolated execution mode if a cleanup flag is set

INTEL CORP50 citations93

US8010731B2Aug 30, 2011

Integrating non-peripheral component interconnect (PCI) resource into a personal computer system

INTEL CORP23 citations92

US7366881B2Apr 29, 2008

Method and apparatus for staggering execution of an instruction

INTEL CORP11 citations92

US6957332B1Oct 18, 2005

Managing a secure platform using a hierarchical executive architecture in isolated execution mode

INTEL CORP31 citations92

US6941458B1Sep 6, 2005

Managing a secure platform using a hierarchical executive architecture in isolated execution mode

INTEL CORP21 citations92

US6480868B2Nov 12, 2002

Conversion from packed floating point data to packed 8-bit integer data in different architectural registers

INTEL CORP37 citations92

US6185670B1Feb 6, 2001

System for reducing number of opcodes required in a processor using an instruction format including operation class code and operation selector code fields

INTEL CORP31 citations92

US7216138B2May 8, 2007

Method and apparatus for floating point operations and format conversion operations

INTEL CORP40 citations91

US6289459B1Sep 11, 2001

Processor unique processor number feature with a user controllable disable capability

INTEL CORP25 citations91

US7594073B2Sep 22, 2009

Method and apparatus for caching memory content on a computing system to facilitate instant-on resuming from a hibernation state

INTEL CORP25 citations86

US7380278B2May 27, 2008

Protecting software environment in isolated execution

INTEL CORP12 citations84

US7111176B1Sep 19, 2006

Generating isolated bus cycles for isolated execution

INTEL CORP16 citations84

US7089418B1Aug 8, 2006

Managing accesses in a processor for isolated execution

INTEL CORP16 citations84

US6970994B2Nov 29, 2005

Executing partial-width packed data instructions

INTEL CORP12 citations84

US6769058B1Jul 27, 2004

Resetting a processor in an isolated execution environment

INTEL CORP18 citations84

Showing the top 50 of 71 patents by PatentIndex Score.

THAKKAR SHREEKANT S

Patents

Controlling access to multiple isolated memories in an isolated execution environment

Controlling access to multiple memory zones in an isolated execution environment

Executing isolated mode instructions in a secure system running in privilege rings

Protecting software environment in isolated execution

Platform and method for issuing and certifying a hardware-protected attestation key

Providing information to a communications device

Generating a key hieararchy for use in an isolated execution environment

Method and apparatus for staggering execution of an instruction

Method and apparatus for efficient vertical SIMD computations

Instruction set extension using prefixes

Method and apparatus for parallel conversion of color values from a single precision floating point format to an integer format

Data conversion between floating point packed format and integer scalar format

System and method for performing an intra-add operation

Integrating non-peripheral component interconnect (PCI) resources into a personal computer system

Managing a secure environment using a chipset in isolated execution mode

Platform and method for remote attestation of a platform

Controlling accesses to isolated memory using a memory controller for isolated execution

Conversion between packed floating point data and packed 32-bit integer data in different architectural registers

Conversion between packed floating point data and packed 32-bit integer data in different architectural registers

Conversion from packed floating point data to packed 8-bit integer data in different architectural registers

Conversion from packed floating point data to packed 16-bit integer data in different architectural registers

Synchronization of weakly ordered write combining operations using a fencing mechanism

Staggering execution of a single packed data instruction using the same circuit

Method and apparatus for converting data format to a graphics card

Method and apparatus for staggering execution of a single packed data instruction using the same circuit

Multi-element operand sub-portion shuffle instruction execution

Method and apparatus for performing integer operations in response to a result of a floating point operation

Platform and method for remote attestation of a platform

Attestation key memory device and bus

Digital watermarks with values derived from remote platforms

File checking using remote signing authority via a network

Managing a secure environment using a chipset in isolated execution mode

Platform and method for generating and utilizing a protected audit log

Attestation key memory device and bus

Controlling access to multiple memory zones in an isolated execution environment

Method and system for scrubbing an isolated area of memory after reset of a processor operating in isolated execution mode if a cleanup flag is set

Integrating non-peripheral component interconnect (PCI) resource into a personal computer system

Method and apparatus for staggering execution of an instruction

Managing a secure platform using a hierarchical executive architecture in isolated execution mode

Managing a secure platform using a hierarchical executive architecture in isolated execution mode

Conversion from packed floating point data to packed 8-bit integer data in different architectural registers

System for reducing number of opcodes required in a processor using an instruction format including operation class code and operation selector code fields

Method and apparatus for floating point operations and format conversion operations

Processor unique processor number feature with a user controllable disable capability

Method and apparatus for caching memory content on a computing system to facilitate instant-on resuming from a hibernation state

Protecting software environment in isolated execution

Generating isolated bus cycles for isolated execution

Managing accesses in a processor for isolated execution

Executing partial-width packed data instructions

Resetting a processor in an isolated execution environment