Inventor

LAUER ISAAC

US193 patents

⚠️ This page may combine multiple inventors who share the name “LAUER ISAAC”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LAUER ISAAC

IBM

Co-integration of silicon and silicon-germanium channels for nanosheet devices

Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer

Non-replacement gate nanomesh field effect transistor with pad regions

Method for fabricating a semiconductor device including gate-to-bulk substrate isolation

Integrated etch stop for capped gate and method for manufacturing the same

Method for making nanosheet CMOS device integrating atomic layer deposition process and replacement gate structure

Diode structure and method for FINFET technologies

Non-replacement gate nanomesh field effect transistor with pad regions

All microwave ZZ control

Co-integration of silicon and silicon-germanium channels for nanosheet devices

Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs

Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer

Integrated etch stop for capped gate and method for manufacturing the same

Method for making nanosheet CMOS device integrating atomic layer deposition process and replacement gate structure

III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology

Methods of forming FINFETs with locally thinned channels from fins having in-situ doped epitaxial cladding

Techniques for dual dielectric thickness for a nanowire CMOS technology using oxygen growth

Wire-last gate-all-around nanowire FET

Epitaxial growth techniques for reducing nanowire dimension and pitch

Nanowire field effect transistor (FET) and method for fabricating the same

Stacked planar double-gate lamellar field-effect transistor

Complementary metal-oxide silicon having silicon and silicon germanium channels

Tuning gate lengths in semiconductor device structures

III-V, Ge, or SiGe fin base lateral bipolar transistor structure and method

Silicidation blocking process using optically sensitive HSQ resist and organic planarizing layer

Diode structure and method for wire-last nanomesh technologies

Diode structure and method for wire-last nanomesh technologies

Wire-last integration method and structure for III-V nanowire devices

Diode structure and method for gate all around silicon nanowire technologies

Diode structure for gate all around silicon nanowire technologies

Structure for self-aligned silicide contacts to an upside-down FET by epitaxial source and drain

Gate electrode optimized for low voltage operation

Non-replacement gate nanomesh field effect transistor with epitixially grown source and drain

Embedded silicon germanium n-type filed effect transistor for reduced floating body effect

CHANG JOSEPHINE B

Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices

Techniques for gate workfunction engineering to reduce short channel effects in planar CMOS devices

Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices

Techniques for metal gate work function engineering to enable multiple threshold voltage nanowire FET devices

Replacement spacer for tunnel FETs

Asymmetric FET formed through use of variable pitch gate for use as logic device and test structure

Nanowire efuses

Techniques for gate workfunction engineering to reduce short channel effects in planar CMOS devices

Techniques for metal gate work function engineering to enable multiple threshold voltage nanowire FET devices

BANGSARUNTIP SARUNYA

Replacement gate fin first wire last gate all around devices

Nanowire tunnel field effect transistors

Gate-all-around nanowire tunnel field effect transistors

DORIS BRUCE B

Tunnel field effect transistor

Tunnel field effect transistor

COHEN GUY

Structure for self-aligned silicide contacts to an upside-down FET by epitaxial source and drain

LAUER ISAAC

Fabrication of a vertical heterojunction tunnel-FET