Inventor
BERGER DEANNA P
US18 patents
⚠️ This page may combine multiple inventors who share the name “BERGER DEANNA P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
14 patentsUS10795824B2Oct 6, 2020
Speculative data return concurrent to an exclusive invalidate request
IBM4 citations73
US9594689B2Mar 14, 2017
Designated cache data backup during system operation
IBM3 citations72
US9898407B2Feb 20, 2018
Configuration based cache coherency protocol selection
IBM3 citations70
US10824565B2Nov 3, 2020
Configuration based cache coherency protocol selection
IBM0 citations51
US10402328B2Sep 3, 2019
Configuration based cache coherency protocol selection
IBM0 citations51
US10394712B2Aug 27, 2019
Configuration based cache coherency protocol selection
IBM0 citations51
US10169260B2Jan 1, 2019
Multiprocessor cache buffer management
IBM0 citations51
US9792213B2Oct 17, 2017
Mitigating busy time in a high performance cache
IBM0 citations51
US9459998B2Oct 4, 2016
Operations interlock under dynamic relocation of storage
IBM1 citations51
US9158694B2Oct 13, 2015
Mitigating busy time in a high performance cache
IBM0 citations51
US8930628B2Jan 6, 2015
Managing in-line store throughput reduction
IBM0 citations51
US9886382B2Feb 6, 2018
Configuration based cache coherency protocol selection
IBM0 citations49
US9892067B2Feb 13, 2018
Multiprocessor cache buffer management
IBM0 citations47
US10379776B2Aug 13, 2019
Operation interlocking in an address-sliced cache system
IBM0 citations40
BERGER DEANNA P
4 patentsUS8447930B2May 21, 2013
Managing in-line store throughput reduction
BERGER DEANNA P2 citations60
US8521960B2Aug 27, 2013
Mitigating busy time in a high performance cache
BERGER DEANNA P1 citations50
US8447932B2May 21, 2013
Recover store data merging
BERGER DEANNA P1 citations49
US8645628B2Feb 4, 2014
Dynamically supporting variable cache array busy and access times for a targeted interleave
BERGER DEANNA P0 citations39