Inventor

KAPLAN DAVID A

US29 patents

⚠️ This page may combine multiple inventors who share the name “KAPLAN DAVID A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KAPLAN DAVID A

ADVANCED MICRO DEVICES INC

Cryptographic protection of information in a processing system

Interrupt virtualization

Platform firmware isolation

Method for privileged mode based secure input mechanism

Hypervisor post-write notification of control and debug register updates

Controlling access by IO devices to pages in a memory in a computing device

Hardware random number generator

Controlling access to pages in a memory in a computing device

Allocating store queue entries to store instructions for early store-to-load forwarding

Leveraging a peripheral device to execute a machine instruction

Storing indications of cleared cache lines

Split random number generator

Using return address predictor to speed up control stack return address verification

System and method for virtualized process isolation including preventing a kernel from accessing user address space

Promoting transactions hitting critical beat of cache line load requests

Hardware based return pointer encryption

Peripheral device protocols in confidential compute architectures

Controlling access to pages in a memory in a computing device

Speculative tablewalk promotion

Controlling access to pages in a memory in a computing device

Unified store queue for reducing linear aliasing effects

SEREBRIN BENJAMIN C

Interrupt virtualization

Programmable atomic memory using stored atomic procedures

Programmable atomic memory using hardware validation agent

KAPLAN DAVID A

Executing micro-code instruction with delay field and address of next instruction which is decoded after indicated delay

Store replay policy

Early branch determination

BRANOVER ALEXANDER J

Methods and apparatus related to processor sleep states

RUPLEY JEFFREY P

Reclaiming physical registers renamed as microcode architectural registers to be available for renaming as instruction set architectural registers based on an active status indicator