Inventor

CHAKRABARTY KRISHNENDU

US25 patents

⚠️ This page may combine multiple inventors who share the name “CHAKRABARTY KRISHNENDU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHAKRABARTY KRISHNENDU

UNIV DUKE

Retiming-based design flow for delay recovery on inter-die paths in 3D ICs

Software-based self-test and diagnosis using on-chip memory

Software-based self-test and diagnosis using on-chip memory

Power switch design and method for reducing leakage power in low-power integrated circuits

Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels

Multi-layer integrated circuits having isolation cells for layer testing and related methods

Signal tracing using on-chip memory for in-system post-fabrication debug

Multi-layer integrated circuits having isolation cells for layer testing and related methods

Signal tracing using on-chip memory for in-system post-fabrication debug

Observation point injection for integrated circuit testing

Scan test of die logic in 3D ICs using TSV probing

Integrated circuit protections against removal and oracle-guided attacks

Software-based self-test and diagnosis using on-chip memory

Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels

Dynamic scan obfuscation for integrated circuit protections

Evaluating functional fault criticality of structural faults for circuit testing

Variation-aware delay fault testing

BHATTACHARYA BHARGAB B

Architectural layout for dilution with reduced wastage in digital microfluidic based lab-on-a-chip

High throughput and volumetric error resilient dilution with digital microfluidic based lab-on-a-chip

NVIDIA CORP

Efficient identification of critical faults in neuromorphic hardware of a neural network

Online fault detection in ReRAM-based AI/ML

GEN MOTORS CORP

Circuit with built-in test and method thereof

ZENG JUN

Print production scheduling

CHAKRABARTY KRISHNENDU

Method and architecture for pre-bond probing of TSVs in 3D stacked integrated circuits

MARVELL INT LTD

Testing monolithic three dimensional integrated circuits