Inventor

PILOLLI LUIGI

IT43 patents

⚠️ This page may combine multiple inventors who share the name “PILOLLI LUIGI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PILOLLI LUIGI

MICRON TECHNOLOGY INC

Systems and methods involving memory-side (NAND-side) write training to improve data valid windows

Memory device distributed controller system

Peak power management in a memory device

Memory device interface communicating with set of data bursts corresponding to memory dies via dedicated portions for command processing

Systems and methods involving write training to improve data valid windows

Apparatus and methods for serializing data output

Data burst suspend mode using multi-level signaling

Memory device deserializer circuit with a reduced form factor

Peak power management in a memory device

Write training in memory devices by adjusting delays based on data patterns

Memory device deserializer circuit with a reduced form factor

Write training in memory devices

Multiple current quantization values for peak power management

Systems and methods involving write training to improve data valid windows

Memories for receiving or transmitting voltage signals

Level shifter with reduced duty cycle variation

Level shifter with reduced duty cycle variation

Apparatus for receiving or transmitting voltage signals

Internal clock signaling

Data burst queue management

Memory dice internal clock

Single node power management for multiple memory devices

Bit error management in memory devices

Methods and apparatus for providing redundancy in memory

Memory devices having distributed controller systems

Chunk definition for partial-page read

Methods for providing redundancy in a memory array comprising mapping portions of data associated with a defective address

Methods for operating a distributed controller system in a memory device

Data burst suspend mode using pause detection

Dual data channel peak power management

Peak power management with data window reservation

Single node power management for multiple memory devices

Data sensing with error correction

Data interleaving module

Write duty cycle calibration on a memory device

LODESTAR LICENSING GROUP LLC

Memory device interface communicating with set of data bursts corresponding to memory dies via dedicated portions for command processing

Memory device interface communicating with set of data bursts corresponding to memory dies via dedicated portions for command processing

INTEL CORP

Techniques to calibrate an impedance level

Read and program operations in a memory device

DE SANTIS LUCA

Memory device distributed controller system

PILOLLI LUIGI

Data interleaving module

MOSCHIANO VIOLANTE

Methods for providing redundancy and apparatuses

SANTIS LUCA DE

Memory device distributed controller system