Inventor

HEINECKE ALEXANDER F

US60 patents

Patents

50 patents

US10990396B2Apr 27, 2021

Systems for performing instructions to quickly convert and use tiles as 1D vectors

INTEL CORP32 citations98

US10719323B2Jul 21, 2020

Systems and methods for performing matrix compress and decompress instructions

INTEL CORP56 citations98

US10896043B2Jan 19, 2021

Systems for performing instructions for fast element unpacking into 2-dimensional registers

INTEL CORP34 citations95

US11977886B2May 7, 2024

Systems and methods for performing instructions specifying ternary tile logic operations

INTEL CORP27 citations94

US10963256B2Mar 30, 2021

Systems and methods for performing instructions to transform matrices into row-interleaved format

INTEL CORP25 citations94

US10963246B2Mar 30, 2021

Systems and methods for performing 16-bit floating-point matrix dot product instructions

INTEL CORP22 citations94

US10866786B2Dec 15, 2020

Systems and methods for performing instructions to transpose rectangular tiles

INTEL CORP27 citations94

US10664287B2May 26, 2020

Systems and methods for implementing chained tile operations

INTEL CORP25 citations94

US12020028B2Jun 25, 2024

Apparatuses, methods, and systems for 8-bit floating-point matrix dot product instructions

INTEL CORP7 citations86

US11972230B2Apr 30, 2024

Matrix transpose and multiply

INTEL CORP9 citations86

US11954489B2Apr 9, 2024

Systems for performing instructions to quickly convert and use tiles as 1D vectors

INTEL CORP9 citations86

US11941395B2Mar 26, 2024

Apparatuses, methods, and systems for instructions for 16-bit floating-point matrix dot product instructions

INTEL CORP7 citations86

US11893389B2Feb 6, 2024

Systems and methods for performing 16-bit floating-point matrix dot product instructions

INTEL CORP7 citations86

US11886875B2Jan 30, 2024

Systems and methods for performing nibble-sized operations on matrix elements

INTEL CORP7 citations86

US11847185B2Dec 19, 2023

Systems and methods of instructions to accelerate multiplication of sparse matrices using bitmasks that identify non-zero elements

INTEL CORP7 citations86

US11748103B2Sep 5, 2023

Systems and methods for performing matrix compress and decompress instructions

INTEL CORP9 citations86

US11714648B2Aug 1, 2023

Systems for performing instructions to quickly convert and use tiles as 1D vectors

INTEL CORP9 citations86

US11614936B2Mar 28, 2023

Systems and methods for performing 16-bit floating-point matrix dot product instructions

INTEL CORP7 citations86

US11579880B2Feb 14, 2023

Systems for performing instructions to quickly convert and use tiles as 1D vectors

INTEL CORP9 citations86

US11579883B2Feb 14, 2023

Systems and methods for performing horizontal tile operations

INTEL CORP17 citations86

US11507376B2Nov 22, 2022

Systems for performing instructions for fast element unpacking into 2-dimensional registers

INTEL CORP10 citations86

US11416260B2Aug 16, 2022

Systems and methods for implementing chained tile operations

INTEL CORP9 citations86

US11403071B2Aug 2, 2022

Systems and methods for performing instructions to transpose rectangular tiles

INTEL CORP7 citations86

US11372643B2Jun 28, 2022

Systems and methods for performing instructions to convert to 16-bit floating-point format

INTEL CORP7 citations86

US11249761B2Feb 15, 2022

Systems and methods for performing matrix compress and decompress instructions

INTEL CORP11 citations86

US10776699B2Sep 15, 2020

Optimized compute hardware for machine learning operations

INTEL CORP10 citations84

US12536020B2Jan 27, 2026

Systems, methods, and apparatuses for tile store

INTEL CORP0 citations73

US12282773B2Apr 22, 2025

Systems, methods, and apparatus for tile configuration

INTEL CORP0 citations73

US12182571B2Dec 31, 2024

Systems, methods, and apparatuses for tile load, multiplication and accumulation

INTEL CORP0 citations73

US12175246B2Dec 24, 2024

Systems and methods for performing matrix compress and decompress instructions

INTEL CORP1 citations73

US11366663B2Jun 21, 2022

Systems and methods for performing 16-bit floating-point vector dot product instructions

INTEL CORP3 citations73

US11334796B2May 17, 2022

Optimized compute hardware for machine learning operations

INTEL CORP2 citations73

US11036504B2Jun 15, 2021

Systems and methods for performing 16-bit floating-point vector dot product instructions

INTEL CORP2 citations73

US10496410B2Dec 3, 2019

Instruction and logic for suppression of hardware prefetchers

INTEL CORP3 citations73

US12287843B2Apr 29, 2025

Systems and methods of instructions to accelerate multiplication of sparse matrices using bitmasks that identify non-zero elements

INTEL CORP1 citations64

US12541365B2Feb 3, 2026

Systems and methods for performing instructions to convert to 16-bit floating-point format

INTEL CORP0 citations63

US12461745B2Nov 4, 2025

Systems for performing instructions to quickly convert and use tiles as 1D vectors

INTEL CORP0 citations63

US12307250B2May 20, 2025

Systems and methods for performing 16-bit floating-point matrix dot product instructions

INTEL CORP0 citations63

US12265826B2Apr 1, 2025

Systems for performing instructions to quickly convert and use tiles as 1D vectors

INTEL CORP0 citations63

US12131154B2Oct 29, 2024

Systems and methods for performing instructions to convert to 16-bit floating-point format

INTEL CORP0 citations63

US12008367B2Jun 11, 2024

Systems and methods for performing 16-bit floating-point vector dot product instructions

INTEL CORP0 citations63

US11954490B2Apr 9, 2024

Systems and methods for performing instructions to transform matrices into row-interleaved format

INTEL CORP0 citations63

US11675590B2Jun 13, 2023

Systems and methods for performing instructions to transform matrices into row-interleaved format

INTEL CORP0 citations63

Showing the top 50 of 60 patents by PatentIndex Score.

HEINECKE ALEXANDER F

Patents

Systems for performing instructions to quickly convert and use tiles as 1D vectors

Systems and methods for performing matrix compress and decompress instructions

Systems for performing instructions for fast element unpacking into 2-dimensional registers

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatus for tile configuration

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatuses for tile load

Systems, methods, and apparatuses for zeroing a matrix

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatus for tile configuration

Systems and methods for performing instructions specifying ternary tile logic operations

Systems and methods for performing instructions to transform matrices into row-interleaved format

Systems and methods for performing 16-bit floating-point matrix dot product instructions

Systems and methods for performing instructions to transpose rectangular tiles

Systems and methods for implementing chained tile operations

Apparatuses, methods, and systems for 8-bit floating-point matrix dot product instructions

Matrix transpose and multiply

Systems for performing instructions to quickly convert and use tiles as 1D vectors

Apparatuses, methods, and systems for instructions for 16-bit floating-point matrix dot product instructions

Systems and methods for performing 16-bit floating-point matrix dot product instructions

Systems and methods for performing nibble-sized operations on matrix elements

Systems and methods of instructions to accelerate multiplication of sparse matrices using bitmasks that identify non-zero elements

Systems and methods for performing matrix compress and decompress instructions

Systems for performing instructions to quickly convert and use tiles as 1D vectors

Systems and methods for performing 16-bit floating-point matrix dot product instructions

Systems for performing instructions to quickly convert and use tiles as 1D vectors

Systems and methods for performing horizontal tile operations

Systems for performing instructions for fast element unpacking into 2-dimensional registers

Systems and methods for implementing chained tile operations

Systems and methods for performing instructions to transpose rectangular tiles

Systems and methods for performing instructions to convert to 16-bit floating-point format

Systems and methods for performing matrix compress and decompress instructions

Optimized compute hardware for machine learning operations

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatus for tile configuration

Systems, methods, and apparatuses for tile load, multiplication and accumulation

Systems and methods for performing matrix compress and decompress instructions

Systems and methods for performing 16-bit floating-point vector dot product instructions

Optimized compute hardware for machine learning operations

Systems and methods for performing 16-bit floating-point vector dot product instructions

Instruction and logic for suppression of hardware prefetchers

Systems and methods of instructions to accelerate multiplication of sparse matrices using bitmasks that identify non-zero elements

Systems and methods for performing instructions to convert to 16-bit floating-point format

Systems for performing instructions to quickly convert and use tiles as 1D vectors

Systems and methods for performing 16-bit floating-point matrix dot product instructions

Systems for performing instructions to quickly convert and use tiles as 1D vectors

Systems and methods for performing instructions to convert to 16-bit floating-point format

Systems and methods for performing 16-bit floating-point vector dot product instructions

Systems and methods for performing instructions to transform matrices into row-interleaved format

Systems and methods for performing instructions to transform matrices into row-interleaved format