Inventor

SADE RAANAN

IL104 patents

⚠️ This page may combine multiple inventors who share the name “SADE RAANAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SADE RAANAN

INTEL CORP

Systems for performing instructions to quickly convert and use tiles as 1D vectors

Systems and methods for performing matrix compress and decompress instructions

Systems for performing instructions for fast element unpacking into 2-dimensional registers

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatus for tile configuration

Systems and methods to load a tile register pair

Systems, methods, and apparatus for tile configuration

Systems and methods to zero a tile register pair

Systems and methods for performing instructions specifying ternary tile logic operations

Systems and methods for performing instructions to transform matrices into row-interleaved format

Systems and methods for performing 16-bit floating-point matrix dot product instructions

Systems and methods for performing instructions to transpose rectangular tiles

Systems for performing instructions to quickly convert and use tiles as 1D vectors

Systems and methods for performing 16-bit floating-point matrix dot product instructions

Systems and methods for performing nibble-sized operations on matrix elements

Systems and methods of instructions to accelerate multiplication of sparse matrices using bitmasks that identify non-zero elements

Systems, methods, and apparatuses for matrix operations

Systems and methods to store a tile register pair to memory

Systems and methods for computing dot products of nibbles in two tile operands

Systems and methods for performing matrix compress and decompress instructions

Systems for performing instructions to quickly convert and use tiles as 1D vectors

Systems, methods, and apparatuses for dot product operations

Systems and methods for performing 16-bit floating-point matrix dot product instructions

Systems and methods to load a tile register pair

Systems and methods for performing horizontal tile operations

Systems for performing instructions to quickly convert and use tiles as 1D vectors

Systems for performing instructions for fast element unpacking into 2-dimensional registers

Systems and methods for performing instructions to transpose rectangular tiles

Systems and methods for performing instructions to convert to 16-bit floating-point format

Systems and methods for performing matrix compress and decompress instructions

Systems and methods to zero a tile register pair

Method and system for performing data movement operations with read snapshot and in place write update

Systems, methods, and apparatuses utilizing CPU storage with a memory reference

Apparatus and method for processing structure of arrays (SoA) and array of structures (AoS) data

Hardware apparatuses and methods for memory corruption detection

Memory corruption detection

Method and system to reduce the power consumption of a memory device

Defining virtualized page attributes based on guest page attributes

Method and system for performing data movement operations with read snapshot and in place write update

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatus for tile configuration

Systems, methods, and apparatuses for tile load, multiplication and accumulation

Systems and methods for performing matrix compress and decompress instructions

Systems, methods, and apparatuses for matrix operations

Hardware apparatuses and methods for memory corruption detection

Systems and methods for performing 16-bit floating-point vector dot product instructions

SHEAFFER GAD

Metaphysical address space for holding lossy metadata in hardware

Extending cache coherency protocols to support locally buffered data

Read and write monitoring attributes in transactional memory (TM) systems

Read and write monitoring attributes in transactional memory (TM) systems