Inventor
ADELMAN MENACHEM
IL57 patents
Patents
50 patentsUS11163565B2Nov 2, 2021
Systems, methods, and apparatuses for dot production operations
INTEL CORP24 citations98
US11086623B2Aug 10, 2021
Systems, methods, and apparatuses for tile matrix multiplication and accumulation
INTEL CORP32 citations98
US11977886B2May 7, 2024
Systems, methods, and apparatuses for tile store
INTEL CORP7 citations94
US11847452B2Dec 19, 2023
Systems, methods, and apparatus for tile configuration
INTEL CORP7 citations94
US11714642B2Aug 1, 2023
Systems, methods, and apparatuses for tile store
INTEL CORP7 citations94
US11567765B2Jan 31, 2023
Systems, methods, and apparatuses for tile load
INTEL CORP8 citations94
US11360770B2Jun 14, 2022
Systems, methods, and apparatuses for zeroing a matrix
INTEL CORP7 citations94
US11288069B2Mar 29, 2022
Systems, methods, and apparatuses for tile store
INTEL CORP7 citations94
US11093247B2Aug 17, 2021
Systems and methods to load a tile register pair
INTEL CORP22 citations94
US11080048B2Aug 3, 2021
Systems, methods, and apparatus for tile configuration
INTEL CORP14 citations94
US11023235B2Jun 1, 2021
Systems and methods to zero a tile register pair
INTEL CORP22 citations94
US10963246B2Mar 30, 2021
Systems and methods for performing 16-bit floating-point matrix dot product instructions
INTEL CORP22 citations94
US11972230B2Apr 30, 2024
Matrix transpose and multiply
INTEL CORP9 citations86
US11941395B2Mar 26, 2024
Apparatuses, methods, and systems for instructions for 16-bit floating-point matrix dot product instructions
INTEL CORP7 citations86
US11893389B2Feb 6, 2024
Systems and methods for performing 16-bit floating-point matrix dot product instructions
INTEL CORP7 citations86
US11816483B2Nov 14, 2023
Systems, methods, and apparatuses for matrix operations
INTEL CORP11 citations86
US11809869B2Nov 7, 2023
Systems and methods to store a tile register pair to memory
INTEL CORP12 citations86
US11669326B2Jun 6, 2023
Systems, methods, and apparatuses for dot product operations
INTEL CORP15 citations86
US11614936B2Mar 28, 2023
Systems and methods for performing 16-bit floating-point matrix dot product instructions
INTEL CORP7 citations86
US11609762B2Mar 21, 2023
Systems and methods to load a tile register pair
INTEL CORP7 citations86
US11372643B2Jun 28, 2022
Systems and methods for performing instructions to convert to 16-bit floating-point format
INTEL CORP7 citations86
US11645077B2May 9, 2023
Systems and methods to zero a tile register pair
INTEL CORP7 citations85
US12536020B2Jan 27, 2026
Systems, methods, and apparatuses for tile store
INTEL CORP0 citations73
US12314717B2May 27, 2025
Systems, methods, and apparatuses for dot production operations
INTEL CORP0 citations73
US12282773B2Apr 22, 2025
Systems, methods, and apparatus for tile configuration
INTEL CORP0 citations73
US12182571B2Dec 31, 2024
Systems, methods, and apparatuses for tile load, multiplication and accumulation
INTEL CORP0 citations73
US12147804B2Nov 19, 2024
Systems, methods, and apparatuses for tile matrix multiplication and accumulation
INTEL CORP1 citations73
US12124847B2Oct 22, 2024
Systems, methods, and apparatuses for tile transpose
INTEL CORP0 citations73
US12106100B2Oct 1, 2024
Systems, methods, and apparatuses for matrix operations
INTEL CORP0 citations73
US11366663B2Jun 21, 2022
Systems and methods for performing 16-bit floating-point vector dot product instructions
INTEL CORP3 citations73
US11036504B2Jun 15, 2021
Systems and methods for performing 16-bit floating-point vector dot product instructions
INTEL CORP2 citations73
US12541365B2Feb 3, 2026
Systems and methods for performing instructions to convert to 16-bit floating-point format
INTEL CORP0 citations63
US12307250B2May 20, 2025
Systems and methods for performing 16-bit floating-point matrix dot product instructions
INTEL CORP0 citations63
US12293186B2May 6, 2025
Systems and methods to store a tile register pair to memory
INTEL CORP0 citations63
US12282525B2Apr 22, 2025
Systems, methods, and apparatuses for matrix operations
INTEL CORP0 citations63
US12236242B2Feb 25, 2025
Systems and methods to load a tile register pair
INTEL CORP0 citations63
US12131154B2Oct 29, 2024
Systems and methods for performing instructions to convert to 16-bit floating-point format
INTEL CORP0 citations63
US12008367B2Jun 11, 2024
Systems and methods for performing 16-bit floating-point vector dot product instructions
INTEL CORP0 citations63
US11263009B2Mar 1, 2022
Systems and methods for performing 16-bit floating-point vector dot product instructions
INTEL CORP0 citations63
US11068263B2Jul 20, 2021
Systems and methods for performing instructions to convert to 16-bit floating-point format
INTEL CORP0 citations63
US11068262B2Jul 20, 2021
Systems and methods for performing instructions to convert to 16-bit floating-point format
INTEL CORP0 citations63
US12405770B2Sep 2, 2025
Matrix transpose and multiply
INTEL CORP0 citations62
US12353878B2Jul 8, 2025
Apparatuses, methods, and systems for instructions for matrix multiplication instructions
INTEL CORP0 citations62
US12112167B2Oct 8, 2024
Matrix data scatter and gather between rows and irregularly spaced memory locations
INTEL CORP0 citations62
US12572359B2Mar 10, 2026
8-bit floating point square root and/or reciprocal square root instructions
INTEL CORP0 citations61
US12086595B2Sep 10, 2024
Apparatuses, methods, and systems for instructions for downconverting a tile row and interleaving with a register
INTEL CORP0 citations61
US12229554B2Feb 18, 2025
BFLOAT16 fused multiply instructions
INTEL CORP0 citations60
US12277419B2Apr 15, 2025
Apparatuses, methods, and systems for instructions to convert 16-bit floating-point formats
INTEL CORP0 citations52
US12524239B2Jan 13, 2026
Systems and methods for performing 8-bit floating-point vector dot product instructions
INTEL CORP0 citations51
US12517728B2Jan 6, 2026
Instructions and support for calculating prefix sums
INTEL CORP0 citations50
Showing the top 50 of 57 patents by PatentIndex Score.